Lines Matching full:clks
77 clocks = <&clks IMX7D_CLK_ARM>;
98 clocks = <&clks IMX7D_USB_PHY1_CLK>;
105 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
172 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
199 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
214 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
249 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
272 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
287 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
406 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
413 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
421 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
429 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
443 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
444 <&clks IMX7D_GPT1_ROOT_CLK>;
452 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
453 <&clks IMX7D_GPT2_ROOT_CLK>;
462 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
463 <&clks IMX7D_GPT3_ROOT_CLK>;
472 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
473 <&clks IMX7D_GPT4_ROOT_CLK>;
482 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
537 clocks = <&clks IMX7D_OCOTP_CLK>;
590 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
604 clocks = <&clks IMX7D_SNVS_CLK>;
612 clocks = <&clks IMX7D_SNVS_CLK>;
620 clks: clock-controller@30380000 { label
682 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
692 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
704 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
705 <&clks IMX7D_ECSPI4_ROOT_CLK>;
717 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
718 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
719 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
720 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
731 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
732 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
733 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
734 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
742 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
743 <&clks IMX7D_PWM1_ROOT_CLK>;
753 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
754 <&clks IMX7D_PWM2_ROOT_CLK>;
764 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
765 <&clks IMX7D_PWM3_ROOT_CLK>;
775 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
776 <&clks IMX7D_PWM4_ROOT_CLK>;
786 clocks = <&clks IMX7D_CLK_DUMMY>,
787 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
788 <&clks IMX7D_CLK_DUMMY>;
803 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
804 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
815 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
816 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
817 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
859 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
860 <&clks IMX7D_ECSPI1_ROOT_CLK>;
871 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
872 <&clks IMX7D_ECSPI2_ROOT_CLK>;
883 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
884 <&clks IMX7D_ECSPI3_ROOT_CLK>;
894 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
895 <&clks IMX7D_UART1_ROOT_CLK>;
905 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
906 <&clks IMX7D_UART2_ROOT_CLK>;
916 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
917 <&clks IMX7D_UART3_ROOT_CLK>;
927 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
928 <&clks IMX7D_SAI1_ROOT_CLK>,
929 <&clks IMX7D_CLK_DUMMY>,
930 <&clks IMX7D_CLK_DUMMY>;
942 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
943 <&clks IMX7D_SAI2_ROOT_CLK>,
944 <&clks IMX7D_CLK_DUMMY>,
945 <&clks IMX7D_CLK_DUMMY>;
957 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
958 <&clks IMX7D_SAI3_ROOT_CLK>,
959 <&clks IMX7D_CLK_DUMMY>,
960 <&clks IMX7D_CLK_DUMMY>;
975 clocks = <&clks IMX7D_CAAM_CLK>,
976 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1002 clocks = <&clks IMX7D_CLK_DUMMY>,
1003 <&clks IMX7D_CAN1_ROOT_CLK>;
1013 clocks = <&clks IMX7D_CLK_DUMMY>,
1014 <&clks IMX7D_CAN2_ROOT_CLK>;
1026 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
1036 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1046 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1056 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1065 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1066 <&clks IMX7D_UART4_ROOT_CLK>;
1076 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1077 <&clks IMX7D_UART5_ROOT_CLK>;
1087 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1088 <&clks IMX7D_UART6_ROOT_CLK>;
1098 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1099 <&clks IMX7D_UART7_ROOT_CLK>;
1108 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1117 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1127 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1139 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1164 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1165 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1166 <&clks IMX7D_USDHC1_ROOT_CLK>;
1176 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1177 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1178 <&clks IMX7D_USDHC2_ROOT_CLK>;
1188 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1189 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1190 <&clks IMX7D_USDHC3_ROOT_CLK>;
1203 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1204 <&clks IMX7D_QSPI_ROOT_CLK>;
1213 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1214 <&clks IMX7D_SDMA_CORE_CLK>;
1228 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1229 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1230 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1231 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1232 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1252 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1263 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1264 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1269 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1270 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;