Lines Matching +full:non +full:- +full:coresight
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
18 clock-frequency = <996000000>;
19 operating-points-v2 = <&cpu0_opp_table>;
20 #cooling-cells = <2>;
21 nvmem-cells = <&fuse_grade>;
22 nvmem-cell-names = "speed_grade";
26 compatible = "arm,cortex-a7";
29 clock-frequency = <996000000>;
30 operating-points-v2 = <&cpu0_opp_table>;
31 #cooling-cells = <2>;
32 cpu-idle-states = <&cpu_sleep_wait>;
37 compatible = "arm,armv7-timer";
38 interrupt-parent = <&intc>;
45 cpu0_opp_table: opp-table {
46 compatible = "operating-points-v2";
47 opp-shared;
49 opp-792000000 {
50 opp-hz = /bits/ 64 <792000000>;
51 opp-microvolt = <1000000>;
52 clock-latency-ns = <150000>;
53 opp-supported-hw = <0xd>, <0x7>;
54 opp-suspend;
57 opp-996000000 {
58 opp-hz = /bits/ 64 <996000000>;
59 opp-microvolt = <1100000>;
60 clock-latency-ns = <150000>;
61 opp-supported-hw = <0xc>, <0x7>;
62 opp-suspend;
65 opp-1200000000 {
66 opp-hz = /bits/ 64 <1200000000>;
67 opp-microvolt = <1225000>;
68 clock-latency-ns = <150000>;
69 opp-supported-hw = <0x8>, <0x3>;
70 opp-suspend;
75 compatible = "usb-nop-xceiv";
77 clock-names = "main_clk";
78 #phy-cells = <0>;
83 compatible = "arm,coresight-etm3x", "arm,primecell";
88 * without arm,primecell-periphid because amba bus try to
91 arm,primecell-periphid = <0xbb956>;
94 clock-names = "apb_pclk";
96 out-ports {
99 remote-endpoint = <&ca_funnel_in_port1>;
105 intc: interrupt-controller@31001000 {
106 compatible = "arm,cortex-a7-gic";
108 #interrupt-cells = <3>;
109 interrupt-controller;
110 interrupt-parent = <&intc>;
120 pcie_phy: pcie-phy@306d0000 {
121 compatible = "fsl,imx7d-pcie-phy";
129 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
135 phy-clkgate-delay-us = <400>;
140 #index-cells = <1>;
141 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
146 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
148 interrupt-names = "int0", "int1", "int2", "pps";
158 clock-names = "ipg", "ahb", "ptp",
160 fsl,num-tx-queues = <3>;
161 fsl,num-rx-queues = <3>;
162 fsl,stop-mode = <&gpr 0x10 4>;
167 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
170 reg-names = "dbi", "config";
171 #address-cells = <3>;
172 #size-cells = <2>;
174 bus-range = <0x00 0xff>;
176 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
177 num-lanes = <1>;
178 num-viewport = <4>;
180 interrupt-names = "msi";
181 #interrupt-cells = <1>;
182 interrupt-map-mask = <0 0 0 0x7>;
187 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
194 clock-names = "pcie", "pcie_bus", "pcie_phy";
195 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
197 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
200 fsl,max-link-speed = <2>;
201 power-domains = <&pgc_pcie_phy>;
205 reset-names = "pciephy", "apps", "turnoff";
206 fsl,imx7d-pcie-phy = <&pcie_phy>;
212 #address-cells = <1>;
213 #size-cells = <0>;
218 remote-endpoint = <&etm1_out_port>;