Lines Matching +full:imx21 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
60 #address-cells = <1>;
61 #size-cells = <0>;
64 compatible = "arm,cortex-a9";
67 next-level-cache = <&L2>;
68 operating-points = <
75 fsl,soc-operating-points = <
82 clock-latency = <61036>; /* two CLK32 periods */
83 #cooling-cells = <2>;
89 clock-names = "arm", "pll2_pfd2_396m", "step",
91 arm-supply = <®_arm>;
92 soc-supply = <®_soc>;
93 nvmem-cells = <&cpu_speed_grade>;
94 nvmem-cell-names = "speed_grade";
98 ckil: clock-ckil {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
112 ipp_di0: clock-ipp-di0 {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0";
119 ipp_di1: clock-ipp-di1 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
126 anaclk1: clock-anaclk1 {
127 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 clock-frequency = <0>;
130 clock-output-names = "anaclk1";
133 anaclk2: clock-anaclk2 {
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <0>;
137 clock-output-names = "anaclk2";
141 compatible = "fsl,imx6sx-mqs";
147 compatible = "arm,cortex-a9-pmu";
148 interrupt-parent = <&gpc>;
153 compatible = "usb-nop-xceiv";
154 #phy-cells = <0>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "simple-bus";
161 interrupt-parent = <&gpc>;
165 compatible = "mmio-sram";
171 compatible = "mmio-sram";
176 intc: interrupt-controller@a01000 {
177 compatible = "arm,cortex-a9-gic";
178 #interrupt-cells = <3>;
179 interrupt-controller;
182 interrupt-parent = <&intc>;
185 L2: cache-controller@a02000 {
186 compatible = "arm,pl310-cache";
189 cache-unified;
190 cache-level = <2>;
191 arm,tag-latency = <4 2 3>;
192 arm,data-latency = <4 2 3>;
202 clock-names = "bus", "core", "shader";
203 power-domains = <&pd_pu>;
206 dma_apbh: dma-apbh@1804000 {
207 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
213 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
214 #dma-cells = <1>;
215 dma-channels = <4>;
219 gpmi: nand-controller@1806000{
220 compatible = "fsl,imx6sx-gpmi-nand";
221 #address-cells = <1>;
222 #size-cells = <1>;
224 reg-names = "gpmi-nand", "bch";
226 interrupt-names = "bch";
232 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
235 dma-names = "rx-tx";
240 compatible = "fsl,aips-bus", "simple-bus";
241 #address-cells = <1>;
242 #size-cells = <1>;
246 spba-bus@2000000 {
247 compatible = "fsl,spba-bus", "simple-bus";
248 #address-cells = <1>;
249 #size-cells = <1>;
254 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
259 dma-names = "rx", "tx";
267 clock-names = "core", "rxtx0",
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
283 clock-names = "ipg", "per";
288 #address-cells = <1>;
289 #size-cells = <0>;
290 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
295 clock-names = "ipg", "per";
300 #address-cells = <1>;
301 #size-cells = <0>;
302 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
307 clock-names = "ipg", "per";
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
319 clock-names = "ipg", "per";
324 compatible = "fsl,imx6sx-uart",
325 "fsl,imx6q-uart", "fsl,imx21-uart";
330 clock-names = "ipg", "per";
332 dma-names = "rx", "tx";
337 compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
345 clock-names = "core", "mem", "extal",
349 dma-names = "rx", "tx";
354 #sound-dai-cells = <0>;
355 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
360 clock-names = "ipg", "baud";
362 dma-names = "rx", "tx";
363 fsl,fifo-depth = <15>;
368 #sound-dai-cells = <0>;
369 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
374 clock-names = "ipg", "baud";
376 dma-names = "rx", "tx";
377 fsl,fifo-depth = <15>;
382 #sound-dai-cells = <0>;
383 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
388 clock-names = "ipg", "baud";
390 dma-names = "rx", "tx";
391 fsl,fifo-depth = <15>;
396 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
406 clock-names = "mem", "ipg", "asrck_0",
414 dma-names = "rxa", "rxb", "rxc",
416 fsl,asrc-rate = <48000>;
417 fsl,asrc-width = <16>;
423 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
428 clock-names = "ipg", "per";
429 #pwm-cells = <3>;
433 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
438 clock-names = "ipg", "per";
439 #pwm-cells = <3>;
443 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
448 clock-names = "ipg", "per";
449 #pwm-cells = <3>;
453 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
458 clock-names = "ipg", "per";
459 #pwm-cells = <3>;
463 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
468 clock-names = "ipg", "per";
469 fsl,stop-mode = <&gpr 0x10 1>;
474 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
479 clock-names = "ipg", "per";
480 fsl,stop-mode = <&gpr 0x10 2>;
485 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
490 clock-names = "ipg", "per";
494 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
498 gpio-controller;
499 #gpio-cells = <2>;
500 interrupt-controller;
501 #interrupt-cells = <2>;
502 gpio-ranges = <&iomuxc 0 5 26>;
506 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
510 gpio-controller;
511 #gpio-cells = <2>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 gpio-ranges = <&iomuxc 0 31 20>;
518 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
522 gpio-controller;
523 #gpio-cells = <2>;
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 gpio-ranges = <&iomuxc 0 51 29>;
530 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
534 gpio-controller;
535 #gpio-cells = <2>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
538 gpio-ranges = <&iomuxc 0 80 32>;
542 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
546 gpio-controller;
547 #gpio-cells = <2>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 gpio-ranges = <&iomuxc 0 112 24>;
554 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
558 gpio-controller;
559 #gpio-cells = <2>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
562 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
566 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
570 gpio-controller;
571 #gpio-cells = <2>;
572 interrupt-controller;
573 #interrupt-cells = <2>;
574 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
578 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
586 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
593 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
600 clks: clock-controller@20c4000 {
601 compatible = "fsl,imx6sx-ccm";
605 #clock-cells = <1>;
607 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
611 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
612 "syscon", "simple-mfd";
618 reg_vdd1p1: regulator-1p1 {
619 compatible = "fsl,anatop-regulator";
620 regulator-name = "vdd1p1";
621 regulator-min-microvolt = <1000000>;
622 regulator-max-microvolt = <1200000>;
623 regulator-always-on;
624 anatop-reg-offset = <0x110>;
625 anatop-vol-bit-shift = <8>;
626 anatop-vol-bit-width = <5>;
627 anatop-min-bit-val = <4>;
628 anatop-min-voltage = <800000>;
629 anatop-max-voltage = <1375000>;
630 anatop-enable-bit = <0>;
633 reg_vdd3p0: regulator-3p0 {
634 compatible = "fsl,anatop-regulator";
635 regulator-name = "vdd3p0";
636 regulator-min-microvolt = <2800000>;
637 regulator-max-microvolt = <3150000>;
638 regulator-always-on;
639 anatop-reg-offset = <0x120>;
640 anatop-vol-bit-shift = <8>;
641 anatop-vol-bit-width = <5>;
642 anatop-min-bit-val = <0>;
643 anatop-min-voltage = <2625000>;
644 anatop-max-voltage = <3400000>;
645 anatop-enable-bit = <0>;
648 reg_vdd2p5: regulator-2p5 {
649 compatible = "fsl,anatop-regulator";
650 regulator-name = "vdd2p5";
651 regulator-min-microvolt = <2250000>;
652 regulator-max-microvolt = <2750000>;
653 regulator-always-on;
654 anatop-reg-offset = <0x130>;
655 anatop-vol-bit-shift = <8>;
656 anatop-vol-bit-width = <5>;
657 anatop-min-bit-val = <0>;
658 anatop-min-voltage = <2100000>;
659 anatop-max-voltage = <2875000>;
660 anatop-enable-bit = <0>;
663 reg_arm: regulator-vddcore {
664 compatible = "fsl,anatop-regulator";
665 regulator-name = "vddarm";
666 regulator-min-microvolt = <725000>;
667 regulator-max-microvolt = <1450000>;
668 regulator-always-on;
669 anatop-reg-offset = <0x140>;
670 anatop-vol-bit-shift = <0>;
671 anatop-vol-bit-width = <5>;
672 anatop-delay-reg-offset = <0x170>;
673 anatop-delay-bit-shift = <24>;
674 anatop-delay-bit-width = <2>;
675 anatop-min-bit-val = <1>;
676 anatop-min-voltage = <725000>;
677 anatop-max-voltage = <1450000>;
680 reg_pcie: regulator-vddpcie {
681 compatible = "fsl,anatop-regulator";
682 regulator-name = "vddpcie";
683 regulator-min-microvolt = <725000>;
684 regulator-max-microvolt = <1450000>;
685 anatop-reg-offset = <0x140>;
686 anatop-vol-bit-shift = <9>;
687 anatop-vol-bit-width = <5>;
688 anatop-delay-reg-offset = <0x170>;
689 anatop-delay-bit-shift = <26>;
690 anatop-delay-bit-width = <2>;
691 anatop-min-bit-val = <1>;
692 anatop-min-voltage = <725000>;
693 anatop-max-voltage = <1450000>;
696 reg_soc: regulator-vddsoc {
697 compatible = "fsl,anatop-regulator";
698 regulator-name = "vddsoc";
699 regulator-min-microvolt = <725000>;
700 regulator-max-microvolt = <1450000>;
701 regulator-always-on;
702 anatop-reg-offset = <0x140>;
703 anatop-vol-bit-shift = <18>;
704 anatop-vol-bit-width = <5>;
705 anatop-delay-reg-offset = <0x170>;
706 anatop-delay-bit-shift = <28>;
707 anatop-delay-bit-width = <2>;
708 anatop-min-bit-val = <1>;
709 anatop-min-voltage = <725000>;
710 anatop-max-voltage = <1450000>;
714 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
715 interrupt-parent = <&gpc>;
718 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
719 nvmem-cell-names = "calib", "temp_grade";
725 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
733 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
741 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
744 snvs_rtc: snvs-rtc-lp {
745 compatible = "fsl,sec-v4.0-mon-rtc-lp";
751 snvs_poweroff: snvs-poweroff {
752 compatible = "syscon-poweroff";
760 snvs_pwrkey: snvs-powerkey {
761 compatible = "fsl,sec-v4.0-pwrkey";
765 wakeup-source;
780 src: reset-controller@20d8000 {
781 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
785 #reset-cells = <1>;
789 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
791 interrupt-controller;
792 #interrupt-cells = <3>;
794 interrupt-parent = <&intc>;
796 clock-names = "ipg";
799 #address-cells = <1>;
800 #size-cells = <0>;
802 power-domain@0 {
804 #power-domain-cells = <0>;
807 pd_pu: power-domain@1 {
809 #power-domain-cells = <0>;
810 power-supply = <®_soc>;
814 pd_disp: power-domain@2 {
816 #power-domain-cells = <0>;
826 pd_pci: power-domain@3 {
828 #power-domain-cells = <0>;
829 power-supply = <®_pcie>;
835 compatible = "fsl,imx6sx-iomuxc";
839 gpr: iomuxc-gpr@20e4000 {
840 compatible = "fsl,imx6sx-iomuxc-gpr",
841 "fsl,imx6q-iomuxc-gpr", "syscon";
846 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
851 clock-names = "ipg", "ahb";
852 #dma-cells = <3>;
854 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
859 compatible = "fsl,aips-bus", "simple-bus";
860 #address-cells = <1>;
861 #size-cells = <1>;
866 compatible = "fsl,sec-v4.0";
867 #address-cells = <1>;
868 #size-cells = <1>;
871 interrupt-parent = <&intc>;
876 clock-names = "mem", "aclk", "ipg", "emi_slow";
879 compatible = "fsl,sec-v4.0-job-ring";
885 compatible = "fsl,sec-v4.0-job-ring";
892 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
899 ahb-burst-config = <0x0>;
900 tx-burst-size-dword = <0x10>;
901 rx-burst-size-dword = <0x10>;
906 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
912 ahb-burst-config = <0x0>;
913 tx-burst-size-dword = <0x10>;
914 rx-burst-size-dword = <0x10>;
919 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
928 ahb-burst-config = <0x0>;
929 tx-burst-size-dword = <0x10>;
930 rx-burst-size-dword = <0x10>;
935 #index-cells = <1>;
936 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
942 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
944 interrupt-names = "int0", "pps";
952 clock-names = "ipg", "ahb", "ptp",
954 fsl,num-tx-queues = <3>;
955 fsl,num-rx-queues = <3>;
956 fsl,stop-mode = <&gpr 0x10 3>;
970 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
976 clock-names = "ipg", "ahb", "per";
977 bus-width = <4>;
982 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
988 clock-names = "ipg", "ahb", "per";
989 bus-width = <4>;
994 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1000 clock-names = "ipg", "ahb", "per";
1001 bus-width = <4>;
1006 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1012 clock-names = "ipg", "ahb", "per";
1013 bus-width = <4>;
1017 i2c1: i2c@21a0000 {
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1020 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1027 i2c2: i2c@21a4000 {
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1037 i2c3: i2c@21a8000 {
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1047 memory-controller@21b0000 {
1048 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1054 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1056 interrupt-names = "int0", "pps";
1064 clock-names = "ipg", "ahb", "ptp",
1066 fsl,stop-mode = <&gpr 0x10 4>;
1071 #address-cells = <2>;
1072 #size-cells = <1>;
1073 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1077 fsl,weim-cs-gpr = <&gpr>;
1082 #address-cells = <1>;
1083 #size-cells = <1>;
1084 compatible = "fsl,imx6sx-ocotp", "syscon";
1088 cpu_speed_grade: speed-grade@10 {
1096 tempmon_temp_grade: temp-grade@20 {
1102 compatible = "fsl,imx6sx-sai";
1108 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1109 dma-names = "rx", "tx";
1115 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1121 compatible = "fsl,imx6sx-sai";
1127 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1128 dma-names = "rx", "tx";
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 compatible = "fsl,imx6sx-qspi";
1138 reg-names = "QuadSPI", "QuadSPI-memory";
1142 clock-names = "qspi_en", "qspi";
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1149 compatible = "fsl,imx6sx-qspi";
1151 reg-names = "QuadSPI", "QuadSPI-memory";
1155 clock-names = "qspi_en", "qspi";
1160 compatible = "fsl,imx6sx-uart",
1161 "fsl,imx6q-uart", "fsl,imx21-uart";
1166 clock-names = "ipg", "per";
1168 dma-names = "rx", "tx";
1173 compatible = "fsl,imx6sx-uart",
1174 "fsl,imx6q-uart", "fsl,imx21-uart";
1179 clock-names = "ipg", "per";
1181 dma-names = "rx", "tx";
1186 compatible = "fsl,imx6sx-uart",
1187 "fsl,imx6q-uart", "fsl,imx21-uart";
1192 clock-names = "ipg", "per";
1194 dma-names = "rx", "tx";
1199 compatible = "fsl,imx6sx-uart",
1200 "fsl,imx6q-uart", "fsl,imx21-uart";
1205 clock-names = "ipg", "per";
1207 dma-names = "rx", "tx";
1211 i2c4: i2c@21f8000 {
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1214 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1223 compatible = "fsl,aips-bus", "simple-bus";
1224 #address-cells = <1>;
1225 #size-cells = <1>;
1229 spba-bus@2240000 {
1230 compatible = "fsl,spba-bus", "simple-bus";
1231 #address-cells = <1>;
1232 #size-cells = <1>;
1242 clock-names = "disp-axi", "csi_mclk", "dcic";
1247 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1251 clock-names = "axi";
1252 power-domains = <&pd_disp>;
1262 clock-names = "disp-axi", "csi_mclk", "dcic";
1267 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1273 clock-names = "pix", "axi", "disp_axi";
1274 power-domains = <&pd_disp>;
1279 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1285 clock-names = "pix", "axi", "disp_axi";
1286 power-domains = <&pd_disp>;
1292 reg-names = "vadc-vafe", "vadc-vdec";
1295 clock-names = "vadc", "csi";
1296 power-domains = <&pd_disp>;
1302 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1306 clock-names = "adc";
1307 fsl,adck-max-frequency = <30000000>, <40000000>,
1313 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1317 clock-names = "adc";
1318 fsl,adck-max-frequency = <30000000>, <40000000>,
1324 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1334 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1339 clock-names = "ipg", "per";
1344 compatible = "fsl,imx6sx-uart",
1345 "fsl,imx6q-uart", "fsl,imx21-uart";
1350 clock-names = "ipg", "per";
1352 dma-names = "rx", "tx";
1357 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1362 clock-names = "ipg", "per";
1363 #pwm-cells = <3>;
1367 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1372 clock-names = "ipg", "per";
1373 #pwm-cells = <3>;
1377 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1382 clock-names = "ipg", "per";
1383 #pwm-cells = <3>;
1387 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1392 clock-names = "ipg", "per";
1393 #pwm-cells = <3>;
1398 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1400 reg-names = "dbi", "config";
1401 #address-cells = <3>;
1402 #size-cells = <2>;
1404 bus-range = <0x00 0xff>;
1406 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1407 num-lanes = <1>;
1409 interrupt-names = "msi";
1410 #interrupt-cells = <1>;
1411 interrupt-map-mask = <0 0 0 0x7>;
1412 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1420 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1421 power-domains = <&pd_disp>, <&pd_pci>;
1422 power-domain-names = "pcie", "pcie_phy";