Lines Matching +full:0 +full:x021b0000
61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
129 clock-frequency = <0>;
135 #clock-cells = <0>;
136 clock-frequency = <0>;
154 #phy-cells = <0>;
166 reg = <0x008f8000 0x4000>;
172 reg = <0x00900000 0x20000>;
180 reg = <0x00a01000 0x1000>,
181 <0x00a00100 0x100>;
187 reg = <0x00a02000 0x1000>;
197 reg = <0x01800000 0x4000>;
208 reg = <0x01804000 0x2000>;
223 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
234 dmas = <&dma_apbh 0>;
243 reg = <0x02000000 0x100000>;
250 reg = <0x02000000 0x40000>;
255 reg = <0x02004000 0x4000>;
257 dmas = <&sdma 14 18 0>,
258 <&sdma 15 18 0>;
263 <&clks 0>, <&clks 0>, <&clks 0>,
265 <&clks 0>, <&clks 0>,
277 #size-cells = <0>;
279 reg = <0x02008000 0x4000>;
289 #size-cells = <0>;
291 reg = <0x0200c000 0x4000>;
301 #size-cells = <0>;
303 reg = <0x02010000 0x4000>;
313 #size-cells = <0>;
315 reg = <0x02014000 0x4000>;
326 reg = <0x02020000 0x4000>;
331 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
338 reg = <0x02024000 0x4000>;
347 dmas = <&sdma 23 21 0>,
348 <&sdma 24 21 0>;
354 #sound-dai-cells = <0>;
356 reg = <0x02028000 0x4000>;
361 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
368 #sound-dai-cells = <0>;
370 reg = <0x0202c000 0x4000>;
375 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
382 #sound-dai-cells = <0>;
384 reg = <0x02030000 0x4000>;
389 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
397 reg = <0x02034000 0x4000>;
400 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
401 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
402 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
403 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
404 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
424 reg = <0x02080000 0x4000>;
434 reg = <0x02084000 0x4000>;
444 reg = <0x02088000 0x4000>;
454 reg = <0x0208c000 0x4000>;
464 reg = <0x02090000 0x4000>;
469 fsl,stop-mode = <&gpr 0x10 1>;
475 reg = <0x02094000 0x4000>;
480 fsl,stop-mode = <&gpr 0x10 2>;
486 reg = <0x02098000 0x4000>;
495 reg = <0x0209c000 0x4000>;
502 gpio-ranges = <&iomuxc 0 5 26>;
507 reg = <0x020a0000 0x4000>;
514 gpio-ranges = <&iomuxc 0 31 20>;
519 reg = <0x020a4000 0x4000>;
526 gpio-ranges = <&iomuxc 0 51 29>;
531 reg = <0x020a8000 0x4000>;
538 gpio-ranges = <&iomuxc 0 80 32>;
543 reg = <0x020ac000 0x4000>;
550 gpio-ranges = <&iomuxc 0 112 24>;
555 reg = <0x020b0000 0x4000>;
562 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
567 reg = <0x020b4000 0x4000>;
574 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
579 reg = <0x020b8000 0x4000>;
587 reg = <0x020bc000 0x4000>;
594 reg = <0x020c0000 0x4000>;
602 reg = <0x020c4000 0x4000>;
613 reg = <0x020c8000 0x1000>;
624 anatop-reg-offset = <0x110>;
630 anatop-enable-bit = <0>;
639 anatop-reg-offset = <0x120>;
642 anatop-min-bit-val = <0>;
645 anatop-enable-bit = <0>;
654 anatop-reg-offset = <0x130>;
657 anatop-min-bit-val = <0>;
660 anatop-enable-bit = <0>;
669 anatop-reg-offset = <0x140>;
670 anatop-vol-bit-shift = <0>;
672 anatop-delay-reg-offset = <0x170>;
685 anatop-reg-offset = <0x140>;
688 anatop-delay-reg-offset = <0x170>;
702 anatop-reg-offset = <0x140>;
705 anatop-delay-reg-offset = <0x170>;
726 reg = <0x020c9000 0x1000>;
734 reg = <0x020ca000 0x1000>;
741 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
742 reg = <0x020cc000 0x4000>;
745 compatible = "fsl,sec-v4.0-mon-rtc-lp";
747 offset = <0x34>;
754 offset = <0x38>;
755 value = <0x60>;
756 mask = <0x60>;
761 compatible = "fsl,sec-v4.0-pwrkey";
771 reg = <0x020d0000 0x4000>;
776 reg = <0x020d4000 0x4000>;
782 reg = <0x020d8000 0x4000>;
790 reg = <0x020dc000 0x4000>;
800 #size-cells = <0>;
802 power-domain@0 {
803 reg = <0>;
804 #power-domain-cells = <0>;
809 #power-domain-cells = <0>;
816 #power-domain-cells = <0>;
828 #power-domain-cells = <0>;
836 reg = <0x020e0000 0x4000>;
842 reg = <0x020e4000 0x4000>;
847 reg = <0x020ec000 0x4000>;
862 reg = <0x02100000 0x100000>;
866 compatible = "fsl,sec-v4.0";
869 reg = <0x2100000 0x10000>;
870 ranges = <0 0x2100000 0x10000>;
879 compatible = "fsl,sec-v4.0-job-ring";
880 reg = <0x1000 0x1000>;
885 compatible = "fsl,sec-v4.0-job-ring";
886 reg = <0x2000 0x1000>;
893 reg = <0x02184000 0x200>;
897 fsl,usbmisc = <&usbmisc 0>;
899 ahb-burst-config = <0x0>;
900 tx-burst-size-dword = <0x10>;
901 rx-burst-size-dword = <0x10>;
907 reg = <0x02184200 0x200>;
912 ahb-burst-config = <0x0>;
913 tx-burst-size-dword = <0x10>;
914 rx-burst-size-dword = <0x10>;
920 reg = <0x02184400 0x200>;
928 ahb-burst-config = <0x0>;
929 tx-burst-size-dword = <0x10>;
930 rx-burst-size-dword = <0x10>;
937 reg = <0x02184800 0x200>;
943 reg = <0x02188000 0x4000>;
956 fsl,stop-mode = <&gpr 0x10 3>;
961 reg = <0x0218c000 0x4000>;
971 reg = <0x02190000 0x4000>;
983 reg = <0x02194000 0x4000>;
995 reg = <0x02198000 0x4000>;
1007 reg = <0x0219c000 0x4000>;
1019 #size-cells = <0>;
1021 reg = <0x021a0000 0x4000>;
1029 #size-cells = <0>;
1031 reg = <0x021a4000 0x4000>;
1039 #size-cells = <0>;
1041 reg = <0x021a8000 0x4000>;
1049 reg = <0x021b0000 0x4000>;
1055 reg = <0x021b4000 0x4000>;
1066 fsl,stop-mode = <&gpr 0x10 4>;
1074 reg = <0x021b8000 0x4000>;
1085 reg = <0x021bc000 0x4000>;
1089 reg = <0x10 4>;
1093 reg = <0x38 4>;
1097 reg = <0x20 4>;
1103 reg = <0x021d4000 0x4000>;
1107 <&clks 0>, <&clks 0>;
1110 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1116 reg = <0x021d8000 0x4000>;
1122 reg = <0x021dc000 0x4000>;
1126 <&clks 0>, <&clks 0>;
1129 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1135 #size-cells = <0>;
1137 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1148 #size-cells = <0>;
1150 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1162 reg = <0x021e8000 0x4000>;
1167 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1175 reg = <0x021ec000 0x4000>;
1180 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1188 reg = <0x021f0000 0x4000>;
1193 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1201 reg = <0x021f4000 0x4000>;
1206 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1213 #size-cells = <0>;
1215 reg = <0x021f8000 0x4000>;
1226 reg = <0x02200000 0x100000>;
1233 reg = <0x02240000 0x40000>;
1237 reg = <0x02214000 0x4000>;
1248 reg = <0x02218000 0x4000>;
1257 reg = <0x0221c000 0x4000>;
1268 reg = <0x02220000 0x4000>;
1280 reg = <0x02224000 0x4000>;
1291 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1303 reg = <0x02280000 0x4000>;
1314 reg = <0x02284000 0x4000>;
1325 reg = <0x02288000 0x4000>;
1333 #size-cells = <0>;
1335 reg = <0x0228c000 0x4000>;
1346 reg = <0x022a0000 0x4000>;
1351 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1358 reg = <0x022a4000 0x4000>;
1368 reg = <0x022a8000 0x4000>;
1378 reg = <0x022ac000 0x4000>;
1388 reg = <0x0022b0000 0x4000>;
1399 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1404 bus-range = <0x00 0xff>;
1405 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
1406 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1411 interrupt-map-mask = <0 0 0 0x7>;
1412 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1413 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1414 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1415 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;