Lines Matching +full:tuning +full:- +full:start +full:- +full:tap
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright 2017-2018 NXP.
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
14 #address-cells = <1>;
15 #size-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
50 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
54 operating-points = <
61 fsl,soc-operating-points = <
62 /* ARM kHz SOC-PU uV */
68 clock-latency = <61036>; /* two CLK32 periods */
69 #cooling-cells = <2>;
75 clock-names = "arm", "pll2_pfd2_396m", "step",
77 nvmem-cells = <&cpu_speed_grade>;
78 nvmem-cell-names = "speed_grade";
82 ckil: clock-ckil {
83 compatible = "fixed-clock";
84 #clock-cells = <0>;
85 clock-frequency = <32768>;
86 clock-output-names = "ckil";
89 osc: clock-osc-24m {
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 clock-frequency = <24000000>;
93 clock-output-names = "osc";
96 ipp_di0: clock-ipp-di0 {
97 compatible = "fixed-clock";
98 #clock-cells = <0>;
99 clock-frequency = <0>;
100 clock-output-names = "ipp_di0";
103 ipp_di1: clock-ipp-di1 {
104 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <0>;
107 clock-output-names = "ipp_di1";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 compatible = "simple-bus";
114 interrupt-parent = <&gpc>;
118 compatible = "mmio-sram";
122 intc: interrupt-controller@a01000 {
123 compatible = "arm,cortex-a9-gic";
124 #interrupt-cells = <3>;
125 interrupt-controller;
128 interrupt-parent = <&intc>;
131 L2: cache-controller@a02000 {
132 compatible = "arm,pl310-cache";
135 cache-unified;
136 cache-level = <2>;
137 arm,tag-latency = <4 2 3>;
138 arm,data-latency = <4 2 3>;
142 compatible = "fsl,aips-bus", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
148 spba: spba-bus@2000000 {
149 compatible = "fsl,spba-bus", "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
156 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
160 dma-names = "rx", "tx";
171 clock-names = "core", "rxtx0",
180 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
184 dma-names = "rx", "tx";
187 clock-names = "ipg", "per";
192 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
196 dma-names = "rx", "tx";
199 clock-names = "ipg", "per";
204 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
208 dma-names = "rx", "tx";
211 clock-names = "ipg", "per";
216 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
220 dma-names = "rx", "tx";
223 clock-names = "ipg", "per";
228 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
229 "fsl,imx21-uart";
233 dma-names = "rx", "tx";
236 clock-names = "ipg", "per";
241 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
242 "fsl,imx21-uart";
246 dma-names = "rx", "tx";
249 clock-names = "ipg", "per";
254 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
255 "fsl,imx21-uart";
259 dma-names = "rx", "tx";
262 clock-names = "ipg", "per";
267 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
271 dma-names = "rx", "tx";
272 fsl,fifo-depth = <15>;
275 clock-names = "ipg", "baud";
280 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
284 dma-names = "rx", "tx";
285 fsl,fifo-depth = <15>;
288 clock-names = "ipg", "baud";
293 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
297 dma-names = "rx", "tx";
298 fsl,fifo-depth = <15>;
301 clock-names = "ipg", "baud";
306 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
307 "fsl,imx21-uart";
311 dma-name = "rx", "tx";
314 clock-names = "ipg", "per";
320 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
325 clock-names = "ipg", "per";
326 #pwm-cells = <3>;
330 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
335 clock-names = "ipg", "per";
336 #pwm-cells = <3>;
340 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
345 clock-names = "ipg", "per";
346 #pwm-cells = <3>;
350 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
355 clock-names = "ipg", "per";
356 #pwm-cells = <3>;
360 compatible = "fsl,imx6sl-gpt";
365 clock-names = "ipg", "per";
369 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
382 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
387 gpio-controller;
388 #gpio-cells = <2>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
391 gpio-ranges = <&iomuxc 0 50 32>;
395 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
400 gpio-controller;
401 #gpio-cells = <2>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
410 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
415 gpio-controller;
416 #gpio-cells = <2>;
417 interrupt-controller;
418 #interrupt-cells = <2>;
419 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
431 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
436 gpio-controller;
437 #gpio-cells = <2>;
438 interrupt-controller;
439 #interrupt-cells = <2>;
440 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
454 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
459 gpio-controller;
460 #gpio-cells = <2>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
466 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
474 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
481 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
488 clks: clock-controller@20c4000 {
489 compatible = "fsl,imx6sll-ccm";
493 #clock-cells = <1>;
495 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
497 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
498 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
502 compatible = "fsl,imx6sll-anatop",
503 "fsl,imx6q-anatop",
504 "syscon", "simple-mfd";
509 #address-cells = <1>;
510 #size-cells = <0>;
512 reg_3p0: regulator-3p0@20c8120 {
513 compatible = "fsl,anatop-regulator";
515 regulator-name = "vdd3p0";
516 regulator-min-microvolt = <2625000>;
517 regulator-max-microvolt = <3400000>;
518 anatop-reg-offset = <0x120>;
519 anatop-vol-bit-shift = <8>;
520 anatop-vol-bit-width = <5>;
521 anatop-min-bit-val = <0>;
522 anatop-min-voltage = <2625000>;
523 anatop-max-voltage = <3400000>;
524 anatop-enable-bit = <0>;
527 tempmon: temperature-sensor {
528 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
530 interrupt-parent = <&gpc>;
532 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
533 nvmem-cell-names = "calib", "temp_grade";
538 usbphy1: usb-phy@20c9000 {
539 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
540 "fsl,imx23-usbphy";
544 phy-3p0-supply = <®_3p0>;
548 usbphy2: usb-phy@20ca000 {
549 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
550 "fsl,imx23-usbphy";
554 phy-reg_3p0-supply = <®_3p0>;
559 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
562 snvs_rtc: snvs-rtc-lp {
563 compatible = "fsl,sec-v4.0-mon-rtc-lp";
570 snvs_poweroff: snvs-poweroff {
571 compatible = "syscon-poweroff";
578 snvs_pwrkey: snvs-powerkey {
579 compatible = "fsl,sec-v4.0-pwrkey";
583 wakeup-source;
588 src: reset-controller@20d8000 {
589 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
593 #reset-cells = <1>;
596 gpc: interrupt-controller@20dc000 {
597 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
599 interrupt-controller;
600 #interrupt-cells = <3>;
602 interrupt-parent = <&intc>;
606 compatible = "fsl,imx6sll-iomuxc";
610 gpr: iomuxc-gpr@20e4000 {
611 compatible = "fsl,imx6sll-iomuxc-gpr",
612 "fsl,imx6q-iomuxc-gpr", "syscon";
617 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
623 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
627 sdma: dma-controller@20ec000 {
628 compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
633 clock-names = "ipg", "ahb";
634 #dma-cells = <3>;
636 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
640 compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
645 clock-names = "axi";
648 lcdif: lcd-controller@20f8000 {
649 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
655 clock-names = "pix", "axi", "disp_axi";
660 compatible = "fsl,imx28-dcp";
666 clock-names = "dcp";
671 compatible = "fsl,aips-bus", "simple-bus";
672 #address-cells = <1>;
673 #size-cells = <1>;
678 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
679 "fsl,imx27-usb";
686 ahb-burst-config = <0x0>;
687 tx-burst-size-dword = <0x10>;
688 rx-burst-size-dword = <0x10>;
693 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
694 "fsl,imx27-usb";
700 ahb-burst-config = <0x0>;
701 tx-burst-size-dword = <0x10>;
702 rx-burst-size-dword = <0x10>;
707 #index-cells = <1>;
708 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
709 "fsl,imx6q-usbmisc";
714 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
720 clock-names = "ipg", "ahb", "per";
721 bus-width = <4>;
722 fsl,tuning-step = <2>;
723 fsl,tuning-start-tap = <20>;
728 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
734 clock-names = "ipg", "ahb", "per";
735 bus-width = <4>;
736 fsl,tuning-step = <2>;
737 fsl,tuning-start-tap = <20>;
742 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
748 clock-names = "ipg", "ahb", "per";
749 bus-width = <4>;
750 fsl,tuning-step = <2>;
751 fsl,tuning-start-tap = <20>;
756 #address-cells = <1>;
757 #size-cells = <0>;
758 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
766 #address-cells = <1>;
767 #size-cells = <0>;
768 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
776 #address-cells = <1>;
777 #size-cells = <0>;
778 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
785 mmdc: memory-controller@21b0000 {
786 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
792 compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
799 #address-cells = <1>;
800 #size-cells = <1>;
801 compatible = "fsl,imx6sll-ocotp", "syscon";
805 cpu_speed_grade: speed-grade@10 {
813 tempmon_temp_grade: temp-grade@20 {
819 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
825 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
826 "fsl,imx21-uart";
830 dma-names = "rx", "tx";
833 clock-names = "ipg", "per";