Lines Matching full:clks
70 clocks = <&clks IMX6SLL_CLK_ARM>,
71 <&clks IMX6SLL_CLK_PLL2_PFD2>,
72 <&clks IMX6SLL_CLK_STEP>,
73 <&clks IMX6SLL_CLK_PLL1_SW>,
74 <&clks IMX6SLL_CLK_PLL1_SYS>;
161 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
162 <&clks IMX6SLL_CLK_OSC>,
163 <&clks IMX6SLL_CLK_SPDIF>,
164 <&clks IMX6SLL_CLK_DUMMY>,
165 <&clks IMX6SLL_CLK_DUMMY>,
166 <&clks IMX6SLL_CLK_DUMMY>,
167 <&clks IMX6SLL_CLK_IPG>,
168 <&clks IMX6SLL_CLK_DUMMY>,
169 <&clks IMX6SLL_CLK_DUMMY>,
170 <&clks IMX6SLL_CLK_SPBA>;
185 clocks = <&clks IMX6SLL_CLK_ECSPI1>,
186 <&clks IMX6SLL_CLK_ECSPI1>;
197 clocks = <&clks IMX6SLL_CLK_ECSPI2>,
198 <&clks IMX6SLL_CLK_ECSPI2>;
209 clocks = <&clks IMX6SLL_CLK_ECSPI3>,
210 <&clks IMX6SLL_CLK_ECSPI3>;
221 clocks = <&clks IMX6SLL_CLK_ECSPI4>,
222 <&clks IMX6SLL_CLK_ECSPI4>;
234 clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
235 <&clks IMX6SLL_CLK_UART4_SERIAL>;
247 clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
248 <&clks IMX6SLL_CLK_UART1_SERIAL>;
260 clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
261 <&clks IMX6SLL_CLK_UART2_SERIAL>;
273 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
274 <&clks IMX6SLL_CLK_SSI1>;
286 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
287 <&clks IMX6SLL_CLK_SSI2>;
299 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
300 <&clks IMX6SLL_CLK_SSI3>;
312 clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
313 <&clks IMX6SLL_CLK_UART3_SERIAL>;
323 clocks = <&clks IMX6SLL_CLK_PWM1>,
324 <&clks IMX6SLL_CLK_PWM1>;
333 clocks = <&clks IMX6SLL_CLK_PWM2>,
334 <&clks IMX6SLL_CLK_PWM2>;
343 clocks = <&clks IMX6SLL_CLK_PWM3>,
344 <&clks IMX6SLL_CLK_PWM3>;
353 clocks = <&clks IMX6SLL_CLK_PWM4>,
354 <&clks IMX6SLL_CLK_PWM4>;
363 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
364 <&clks IMX6SLL_CLK_GPT_SERIAL>;
373 clocks = <&clks IMX6SLL_CLK_GPIO1>;
386 clocks = <&clks IMX6SLL_CLK_GPIO2>;
399 clocks = <&clks IMX6SLL_CLK_GPIO3>;
414 clocks = <&clks IMX6SLL_CLK_GPIO4>;
435 clocks = <&clks IMX6SLL_CLK_GPIO5>;
458 clocks = <&clks IMX6SLL_CLK_GPIO6>;
469 clocks = <&clks IMX6SLL_CLK_KPP>;
477 clocks = <&clks IMX6SLL_CLK_WDOG1>;
484 clocks = <&clks IMX6SLL_CLK_WDOG2>;
488 clks: clock-controller@20c4000 { label
497 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
498 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
534 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
543 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
553 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
620 clocks = <&clks IMX6SLL_CLK_DUMMY>,
621 <&clks IMX6SLL_CLK_CSI>,
622 <&clks IMX6SLL_CLK_DUMMY>;
631 clocks = <&clks IMX6SLL_CLK_IPG>,
632 <&clks IMX6SLL_CLK_SDMA>;
644 clocks = <&clks IMX6SLL_CLK_PXP>;
652 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
653 <&clks IMX6SLL_CLK_LCDIF_APB>,
654 <&clks IMX6SLL_CLK_DUMMY>;
665 clocks = <&clks IMX6SLL_CLK_DCP>;
682 clocks = <&clks IMX6SLL_CLK_USBOH3>;
697 clocks = <&clks IMX6SLL_CLK_USBOH3>;
717 clocks = <&clks IMX6SLL_CLK_USDHC1>,
718 <&clks IMX6SLL_CLK_USDHC1>,
719 <&clks IMX6SLL_CLK_USDHC1>;
731 clocks = <&clks IMX6SLL_CLK_USDHC2>,
732 <&clks IMX6SLL_CLK_USDHC2>,
733 <&clks IMX6SLL_CLK_USDHC2>;
745 clocks = <&clks IMX6SLL_CLK_USDHC3>,
746 <&clks IMX6SLL_CLK_USDHC3>,
747 <&clks IMX6SLL_CLK_USDHC3>;
761 clocks = <&clks IMX6SLL_CLK_I2C1>;
771 clocks = <&clks IMX6SLL_CLK_I2C2>;
781 clocks = <&clks IMX6SLL_CLK_I2C3>;
788 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
795 clocks = <&clks IMX6SLL_CLK_DUMMY>;
803 clocks = <&clks IMX6SLL_CLK_OCOTP>;
831 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
832 <&clks IMX6SLL_CLK_UART5_SERIAL>;