Lines Matching +full:imx21 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
51 #size-cells = <0>;
54 compatible = "arm,cortex-a9";
57 next-level-cache = <&L2>;
58 operating-points = <
64 fsl,soc-operating-points = <
65 /* ARM kHz SOC-PU uV */
70 clock-latency = <61036>; /* two CLK32 periods */
71 #cooling-cells = <2>;
75 clock-names = "arm", "pll2_pfd2_396m", "step",
77 arm-supply = <®_arm>;
78 pu-supply = <®_pu>;
79 soc-supply = <®_soc>;
80 nvmem-cells = <&cpu_speed_grade>;
81 nvmem-cell-names = "speed_grade";
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <32768>;
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <24000000>;
100 compatible = "arm,cortex-a9-pmu";
101 interrupt-parent = <&gpc>;
106 compatible = "usb-nop-xceiv";
107 #phy-cells = <0>;
111 #address-cells = <1>;
112 #size-cells = <1>;
113 compatible = "simple-bus";
114 interrupt-parent = <&gpc>;
118 compatible = "mmio-sram";
123 intc: interrupt-controller@a01000 {
124 compatible = "arm,cortex-a9-gic";
125 #interrupt-cells = <3>;
126 interrupt-controller;
129 interrupt-parent = <&intc>;
132 L2: cache-controller@a02000 {
133 compatible = "arm,pl310-cache";
136 cache-unified;
137 cache-level = <2>;
138 arm,tag-latency = <4 2 3>;
139 arm,data-latency = <4 2 3>;
143 compatible = "fsl,aips-bus", "simple-bus";
144 #address-cells = <1>;
145 #size-cells = <1>;
149 spba: spba-bus@2000000 {
150 compatible = "fsl,spba-bus", "simple-bus";
151 #address-cells = <1>;
152 #size-cells = <1>;
157 compatible = "fsl,imx6sl-spdif",
158 "fsl,imx35-spdif";
163 dma-names = "rx", "tx";
169 clock-names = "core", "rxtx0",
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
185 clock-names = "ipg", "per";
190 #address-cells = <1>;
191 #size-cells = <0>;
192 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
197 clock-names = "ipg", "per";
202 #address-cells = <1>;
203 #size-cells = <0>;
204 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
209 clock-names = "ipg", "per";
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
221 clock-names = "ipg", "per";
226 compatible = "fsl,imx6sl-uart",
227 "fsl,imx6q-uart", "fsl,imx21-uart";
232 clock-names = "ipg", "per";
234 dma-names = "rx", "tx";
239 compatible = "fsl,imx6sl-uart",
240 "fsl,imx6q-uart", "fsl,imx21-uart";
245 clock-names = "ipg", "per";
247 dma-names = "rx", "tx";
252 compatible = "fsl,imx6sl-uart",
253 "fsl,imx6q-uart", "fsl,imx21-uart";
258 clock-names = "ipg", "per";
260 dma-names = "rx", "tx";
265 #sound-dai-cells = <0>;
266 compatible = "fsl,imx6sl-ssi",
267 "fsl,imx51-ssi";
272 clock-names = "ipg", "baud";
275 dma-names = "rx", "tx";
276 fsl,fifo-depth = <15>;
281 #sound-dai-cells = <0>;
282 compatible = "fsl,imx6sl-ssi",
283 "fsl,imx51-ssi";
288 clock-names = "ipg", "baud";
291 dma-names = "rx", "tx";
292 fsl,fifo-depth = <15>;
297 #sound-dai-cells = <0>;
298 compatible = "fsl,imx6sl-ssi",
299 "fsl,imx51-ssi";
304 clock-names = "ipg", "baud";
307 dma-names = "rx", "tx";
308 fsl,fifo-depth = <15>;
313 compatible = "fsl,imx6sl-uart",
314 "fsl,imx6q-uart", "fsl,imx21-uart";
319 clock-names = "ipg", "per";
321 dma-names = "rx", "tx";
326 compatible = "fsl,imx6sl-uart",
327 "fsl,imx6q-uart", "fsl,imx21-uart";
332 clock-names = "ipg", "per";
334 dma-names = "rx", "tx";
340 #pwm-cells = <3>;
341 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
346 clock-names = "ipg", "per";
350 #pwm-cells = <3>;
351 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
356 clock-names = "ipg", "per";
360 #pwm-cells = <3>;
361 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
366 clock-names = "ipg", "per";
370 #pwm-cells = <3>;
371 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
376 clock-names = "ipg", "per";
380 compatible = "fsl,imx6sl-gpt";
385 clock-names = "ipg", "per";
389 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
393 gpio-controller;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
406 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
410 gpio-controller;
411 #gpio-cells = <2>;
412 interrupt-controller;
413 #interrupt-cells = <2>;
414 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
424 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
428 gpio-controller;
429 #gpio-cells = <2>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
443 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
447 gpio-controller;
448 #gpio-cells = <2>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
451 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
469 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
473 gpio-controller;
474 #gpio-cells = <2>;
475 interrupt-controller;
476 #interrupt-cells = <2>;
477 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
491 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
499 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
506 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
513 clks: clock-controller@20c4000 {
514 compatible = "fsl,imx6sl-ccm";
518 #clock-cells = <1>;
522 compatible = "fsl,imx6sl-anatop",
523 "fsl,imx6q-anatop",
524 "syscon", "simple-mfd";
530 reg_vdd1p1: regulator-1p1 {
531 compatible = "fsl,anatop-regulator";
532 regulator-name = "vdd1p1";
533 regulator-min-microvolt = <1000000>;
534 regulator-max-microvolt = <1200000>;
535 regulator-always-on;
536 anatop-reg-offset = <0x110>;
537 anatop-vol-bit-shift = <8>;
538 anatop-vol-bit-width = <5>;
539 anatop-min-bit-val = <4>;
540 anatop-min-voltage = <800000>;
541 anatop-max-voltage = <1375000>;
542 anatop-enable-bit = <0>;
545 reg_vdd3p0: regulator-3p0 {
546 compatible = "fsl,anatop-regulator";
547 regulator-name = "vdd3p0";
548 regulator-min-microvolt = <2800000>;
549 regulator-max-microvolt = <3150000>;
550 regulator-always-on;
551 anatop-reg-offset = <0x120>;
552 anatop-vol-bit-shift = <8>;
553 anatop-vol-bit-width = <5>;
554 anatop-min-bit-val = <0>;
555 anatop-min-voltage = <2625000>;
556 anatop-max-voltage = <3400000>;
557 anatop-enable-bit = <0>;
560 reg_vdd2p5: regulator-2p5 {
561 compatible = "fsl,anatop-regulator";
562 regulator-name = "vdd2p5";
563 regulator-min-microvolt = <2250000>;
564 regulator-max-microvolt = <2750000>;
565 regulator-always-on;
566 anatop-reg-offset = <0x130>;
567 anatop-vol-bit-shift = <8>;
568 anatop-vol-bit-width = <5>;
569 anatop-min-bit-val = <0>;
570 anatop-min-voltage = <2100000>;
571 anatop-max-voltage = <2850000>;
572 anatop-enable-bit = <0>;
575 reg_arm: regulator-vddcore {
576 compatible = "fsl,anatop-regulator";
577 regulator-name = "vddarm";
578 regulator-min-microvolt = <725000>;
579 regulator-max-microvolt = <1450000>;
580 regulator-always-on;
581 anatop-reg-offset = <0x140>;
582 anatop-vol-bit-shift = <0>;
583 anatop-vol-bit-width = <5>;
584 anatop-delay-reg-offset = <0x170>;
585 anatop-delay-bit-shift = <24>;
586 anatop-delay-bit-width = <2>;
587 anatop-min-bit-val = <1>;
588 anatop-min-voltage = <725000>;
589 anatop-max-voltage = <1450000>;
592 reg_pu: regulator-vddpu {
593 compatible = "fsl,anatop-regulator";
594 regulator-name = "vddpu";
595 regulator-min-microvolt = <725000>;
596 regulator-max-microvolt = <1450000>;
597 anatop-reg-offset = <0x140>;
598 anatop-vol-bit-shift = <9>;
599 anatop-vol-bit-width = <5>;
600 anatop-delay-reg-offset = <0x170>;
601 anatop-delay-bit-shift = <26>;
602 anatop-delay-bit-width = <2>;
603 anatop-min-bit-val = <1>;
604 anatop-min-voltage = <725000>;
605 anatop-max-voltage = <1450000>;
608 reg_soc: regulator-vddsoc {
609 compatible = "fsl,anatop-regulator";
610 regulator-name = "vddsoc";
611 regulator-min-microvolt = <725000>;
612 regulator-max-microvolt = <1450000>;
613 regulator-always-on;
614 anatop-reg-offset = <0x140>;
615 anatop-vol-bit-shift = <18>;
616 anatop-vol-bit-width = <5>;
617 anatop-delay-reg-offset = <0x170>;
618 anatop-delay-bit-shift = <28>;
619 anatop-delay-bit-width = <2>;
620 anatop-min-bit-val = <1>;
621 anatop-min-voltage = <725000>;
622 anatop-max-voltage = <1450000>;
626 compatible = "fsl,imx6q-tempmon";
628 interrupt-parent = <&gpc>;
630 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
631 nvmem-cell-names = "calib", "temp_grade";
637 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
645 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
653 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
656 snvs_rtc: snvs-rtc-lp {
657 compatible = "fsl,sec-v4.0-mon-rtc-lp";
664 snvs_poweroff: snvs-poweroff {
665 compatible = "syscon-poweroff";
684 src: reset-controller@20d8000 {
685 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
689 #reset-cells = <1>;
693 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
695 interrupt-controller;
696 #interrupt-cells = <3>;
698 interrupt-parent = <&intc>;
700 clock-names = "ipg";
703 #address-cells = <1>;
704 #size-cells = <0>;
706 power-domain@0 {
708 #power-domain-cells = <0>;
711 pd_pu: power-domain@1 {
713 #power-domain-cells = <0>;
714 power-supply = <®_pu>;
719 pd_disp: power-domain@2 {
721 #power-domain-cells = <0>;
731 gpr: iomuxc-gpr@20e0000 {
732 compatible = "fsl,imx6sl-iomuxc-gpr",
733 "fsl,imx6q-iomuxc-gpr", "syscon";
738 compatible = "fsl,imx6sl-iomuxc";
753 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
758 clock-names = "ipg", "ahb";
759 #dma-cells = <3>;
761 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
775 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
781 clock-names = "pix", "axi", "disp_axi";
783 power-domains = <&pd_disp>;
787 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
796 compatible = "fsl,aips-bus", "simple-bus";
797 #address-cells = <1>;
798 #size-cells = <1>;
803 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
809 ahb-burst-config = <0x0>;
810 tx-burst-size-dword = <0x10>;
811 rx-burst-size-dword = <0x10>;
816 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
822 ahb-burst-config = <0x0>;
823 tx-burst-size-dword = <0x10>;
824 rx-burst-size-dword = <0x10>;
829 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
837 ahb-burst-config = <0x0>;
838 tx-burst-size-dword = <0x10>;
839 rx-burst-size-dword = <0x10>;
844 #index-cells = <1>;
845 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
851 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
856 clock-names = "ipg", "ahb";
861 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
867 clock-names = "ipg", "ahb", "per";
868 bus-width = <4>;
873 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
879 clock-names = "ipg", "ahb", "per";
880 bus-width = <4>;
885 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
891 clock-names = "ipg", "ahb", "per";
892 bus-width = <4>;
897 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
903 clock-names = "ipg", "ahb", "per";
904 bus-width = <4>;
908 i2c1: i2c@21a0000 {
909 #address-cells = <1>;
910 #size-cells = <0>;
911 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
918 i2c2: i2c@21a4000 {
919 #address-cells = <1>;
920 #size-cells = <0>;
921 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
928 i2c3: i2c@21a8000 {
929 #address-cells = <1>;
930 #size-cells = <0>;
931 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
938 memory-controller@21b0000 {
939 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
945 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
952 #address-cells = <2>;
953 #size-cells = <1>;
956 fsl,weim-cs-gpr = <&gpr>;
961 compatible = "fsl,imx6sl-ocotp", "syscon";
964 #address-cells = <1>;
965 #size-cells = <1>;
967 cpu_speed_grade: speed-grade@10 {
975 tempmon_temp_grade: temp-grade@20 {
981 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
993 clock-names = "bus", "core";
994 power-domains = <&pd_pu>;
1003 clock-names = "bus", "core";
1004 power-domains = <&pd_pu>;