Lines Matching +full:imx53 +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fsl,imx-ckil", "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
64 compatible = "fsl,imx-ckih1", "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
70 compatible = "fsl,imx-osc", "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <24000000>;
77 #address-cells = <1>;
78 #size-cells = <0>;
79 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
83 lvds-channel@0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
93 remote-endpoint = <&ipu1_di0_lvds0>;
101 remote-endpoint = <&ipu1_di1_lvds0>;
106 lvds-channel@1 {
107 #address-cells = <1>;
108 #size-cells = <0>;
116 remote-endpoint = <&ipu1_di0_lvds1>;
124 remote-endpoint = <&ipu1_di1_lvds1>;
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&gpc>;
137 compatible = "usb-nop-xceiv";
138 #phy-cells = <0>;
142 compatible = "usb-nop-xceiv";
143 #phy-cells = <0>;
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "simple-bus";
150 interrupt-parent = <&gpc>;
153 dma_apbh: dma-apbh@110000 {
154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
160 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
161 #dma-cells = <1>;
162 dma-channels = <4>;
166 gpmi: nand-controller@112000 {
167 compatible = "fsl,imx6q-gpmi-nand";
169 reg-names = "gpmi-nand", "bch";
171 interrupt-names = "bch";
177 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
180 dma-names = "rx-tx";
190 clock-names = "iahb", "isfr";
194 #address-cells = <1>;
195 #size-cells = <0>;
201 remote-endpoint = <&ipu1_di0_hdmi>;
209 remote-endpoint = <&ipu1_di1_hdmi>;
222 clock-names = "bus", "core", "shader";
223 power-domains = <&pd_pu>;
224 #cooling-cells = <2>;
233 clock-names = "bus", "core";
234 power-domains = <&pd_pu>;
235 #cooling-cells = <2>;
239 compatible = "arm,cortex-a9-twd-timer";
242 interrupt-parent = <&intc>;
246 intc: interrupt-controller@a01000 {
247 compatible = "arm,cortex-a9-gic";
248 #interrupt-cells = <3>;
249 interrupt-controller;
252 interrupt-parent = <&intc>;
255 L2: cache-controller@a02000 {
256 compatible = "arm,pl310-cache";
259 cache-unified;
260 cache-level = <2>;
261 arm,tag-latency = <4 2 3>;
262 arm,data-latency = <4 2 3>;
263 arm,shared-override;
267 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
270 reg-names = "dbi", "config";
271 #address-cells = <3>;
272 #size-cells = <2>;
274 bus-range = <0x00 0xff>;
276 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
277 num-lanes = <1>;
278 num-viewport = <4>;
280 interrupt-names = "msi";
281 #interrupt-cells = <1>;
282 interrupt-map-mask = <0 0 0 0x7>;
283 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
290 clock-names = "pcie", "pcie_bus", "pcie_phy";
295 compatible = "fsl,aips-bus", "simple-bus";
296 #address-cells = <1>;
297 #size-cells = <1>;
301 spba-bus@2000000 {
302 compatible = "fsl,spba-bus", "simple-bus";
303 #address-cells = <1>;
304 #size-cells = <1>;
309 compatible = "fsl,imx35-spdif";
314 dma-names = "rx", "tx";
320 clock-names = "core", "rxtx0",
329 #address-cells = <1>;
330 #size-cells = <0>;
331 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
336 clock-names = "ipg", "per";
338 dma-names = "rx", "tx";
343 #address-cells = <1>;
344 #size-cells = <0>;
345 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
350 clock-names = "ipg", "per";
352 dma-names = "rx", "tx";
357 #address-cells = <1>;
358 #size-cells = <0>;
359 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
364 clock-names = "ipg", "per";
366 dma-names = "rx", "tx";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
378 clock-names = "ipg", "per";
380 dma-names = "rx", "tx";
385 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
390 clock-names = "ipg", "per";
392 dma-names = "rx", "tx";
397 #sound-dai-cells = <0>;
398 compatible = "fsl,imx35-esai";
406 clock-names = "core", "mem", "extal", "fsys", "spba";
408 dma-names = "rx", "tx";
413 #sound-dai-cells = <0>;
414 compatible = "fsl,imx6q-ssi",
415 "fsl,imx51-ssi";
420 clock-names = "ipg", "baud";
423 dma-names = "rx", "tx";
424 fsl,fifo-depth = <15>;
429 #sound-dai-cells = <0>;
430 compatible = "fsl,imx6q-ssi",
431 "fsl,imx51-ssi";
436 clock-names = "ipg", "baud";
439 dma-names = "rx", "tx";
440 fsl,fifo-depth = <15>;
445 #sound-dai-cells = <0>;
446 compatible = "fsl,imx6q-ssi",
447 "fsl,imx51-ssi";
452 clock-names = "ipg", "baud";
455 dma-names = "rx", "tx";
456 fsl,fifo-depth = <15>;
461 compatible = "fsl,imx53-asrc";
471 clock-names = "mem", "ipg", "asrck_0",
478 dma-names = "rxa", "rxb", "rxc",
480 fsl,asrc-rate = <48000>;
481 fsl,asrc-width = <16>;
495 interrupt-names = "bit", "jpeg";
498 clock-names = "per", "ahb";
499 power-domains = <&pd_pu>;
509 #pwm-cells = <3>;
510 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
515 clock-names = "ipg", "per";
520 #pwm-cells = <3>;
521 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
526 clock-names = "ipg", "per";
531 #pwm-cells = <3>;
532 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
537 clock-names = "ipg", "per";
542 #pwm-cells = <3>;
543 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
548 clock-names = "ipg", "per";
553 compatible = "fsl,imx6q-flexcan";
558 clock-names = "ipg", "per";
559 fsl,stop-mode = <&gpr 0x34 28>;
564 compatible = "fsl,imx6q-flexcan";
569 clock-names = "ipg", "per";
570 fsl,stop-mode = <&gpr 0x34 29>;
575 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
581 clock-names = "ipg", "per", "osc_per";
585 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
589 gpio-controller;
590 #gpio-cells = <2>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
596 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
600 gpio-controller;
601 #gpio-cells = <2>;
602 interrupt-controller;
603 #interrupt-cells = <2>;
607 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
611 gpio-controller;
612 #gpio-cells = <2>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
618 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
622 gpio-controller;
623 #gpio-cells = <2>;
624 interrupt-controller;
625 #interrupt-cells = <2>;
629 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
633 gpio-controller;
634 #gpio-cells = <2>;
635 interrupt-controller;
636 #interrupt-cells = <2>;
640 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
644 gpio-controller;
645 #gpio-cells = <2>;
646 interrupt-controller;
647 #interrupt-cells = <2>;
651 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
655 gpio-controller;
656 #gpio-cells = <2>;
657 interrupt-controller;
658 #interrupt-cells = <2>;
662 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
670 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
677 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
684 clks: clock-controller@20c4000 {
685 compatible = "fsl,imx6q-ccm";
689 #clock-cells = <1>;
693 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
699 reg_vdd1p1: regulator-1p1 {
700 compatible = "fsl,anatop-regulator";
701 regulator-name = "vdd1p1";
702 regulator-min-microvolt = <1000000>;
703 regulator-max-microvolt = <1200000>;
704 regulator-always-on;
705 anatop-reg-offset = <0x110>;
706 anatop-vol-bit-shift = <8>;
707 anatop-vol-bit-width = <5>;
708 anatop-min-bit-val = <4>;
709 anatop-min-voltage = <800000>;
710 anatop-max-voltage = <1375000>;
711 anatop-enable-bit = <0>;
714 reg_vdd3p0: regulator-3p0 {
715 compatible = "fsl,anatop-regulator";
716 regulator-name = "vdd3p0";
717 regulator-min-microvolt = <2800000>;
718 regulator-max-microvolt = <3150000>;
719 regulator-always-on;
720 anatop-reg-offset = <0x120>;
721 anatop-vol-bit-shift = <8>;
722 anatop-vol-bit-width = <5>;
723 anatop-min-bit-val = <0>;
724 anatop-min-voltage = <2625000>;
725 anatop-max-voltage = <3400000>;
726 anatop-enable-bit = <0>;
729 reg_vdd2p5: regulator-2p5 {
730 compatible = "fsl,anatop-regulator";
731 regulator-name = "vdd2p5";
732 regulator-min-microvolt = <2250000>;
733 regulator-max-microvolt = <2750000>;
734 regulator-always-on;
735 anatop-reg-offset = <0x130>;
736 anatop-vol-bit-shift = <8>;
737 anatop-vol-bit-width = <5>;
738 anatop-min-bit-val = <0>;
739 anatop-min-voltage = <2100000>;
740 anatop-max-voltage = <2875000>;
741 anatop-enable-bit = <0>;
744 reg_arm: regulator-vddcore {
745 compatible = "fsl,anatop-regulator";
746 regulator-name = "vddarm";
747 regulator-min-microvolt = <725000>;
748 regulator-max-microvolt = <1450000>;
749 regulator-always-on;
750 anatop-reg-offset = <0x140>;
751 anatop-vol-bit-shift = <0>;
752 anatop-vol-bit-width = <5>;
753 anatop-delay-reg-offset = <0x170>;
754 anatop-delay-bit-shift = <24>;
755 anatop-delay-bit-width = <2>;
756 anatop-min-bit-val = <1>;
757 anatop-min-voltage = <725000>;
758 anatop-max-voltage = <1450000>;
761 reg_pu: regulator-vddpu {
762 compatible = "fsl,anatop-regulator";
763 regulator-name = "vddpu";
764 regulator-min-microvolt = <725000>;
765 regulator-max-microvolt = <1450000>;
766 regulator-enable-ramp-delay = <150>;
767 anatop-reg-offset = <0x140>;
768 anatop-vol-bit-shift = <9>;
769 anatop-vol-bit-width = <5>;
770 anatop-delay-reg-offset = <0x170>;
771 anatop-delay-bit-shift = <26>;
772 anatop-delay-bit-width = <2>;
773 anatop-min-bit-val = <1>;
774 anatop-min-voltage = <725000>;
775 anatop-max-voltage = <1450000>;
778 reg_soc: regulator-vddsoc {
779 compatible = "fsl,anatop-regulator";
780 regulator-name = "vddsoc";
781 regulator-min-microvolt = <725000>;
782 regulator-max-microvolt = <1450000>;
783 regulator-always-on;
784 anatop-reg-offset = <0x140>;
785 anatop-vol-bit-shift = <18>;
786 anatop-vol-bit-width = <5>;
787 anatop-delay-reg-offset = <0x170>;
788 anatop-delay-bit-shift = <28>;
789 anatop-delay-bit-width = <2>;
790 anatop-min-bit-val = <1>;
791 anatop-min-voltage = <725000>;
792 anatop-max-voltage = <1450000>;
796 compatible = "fsl,imx6q-tempmon";
797 interrupt-parent = <&gpc>;
800 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
801 nvmem-cell-names = "calib", "temp_grade";
803 #thermal-sensor-cells = <0>;
808 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
816 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
824 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
827 snvs_rtc: snvs-rtc-lp {
828 compatible = "fsl,sec-v4.0-mon-rtc-lp";
835 snvs_poweroff: snvs-poweroff {
836 compatible = "syscon-poweroff";
844 snvs_pwrkey: snvs-powerkey {
845 compatible = "fsl,sec-v4.0-pwrkey";
849 wakeup-source;
853 snvs_lpgpr: snvs-lpgpr {
854 compatible = "fsl,imx6q-snvs-lpgpr";
868 src: reset-controller@20d8000 {
869 compatible = "fsl,imx6q-src", "fsl,imx51-src";
873 #reset-cells = <1>;
877 compatible = "fsl,imx6q-gpc";
879 interrupt-controller;
880 #interrupt-cells = <3>;
882 interrupt-parent = <&intc>;
884 clock-names = "ipg";
887 #address-cells = <1>;
888 #size-cells = <0>;
890 power-domain@0 {
892 #power-domain-cells = <0>;
894 pd_pu: power-domain@1 {
896 #power-domain-cells = <0>;
897 power-supply = <®_pu>;
908 gpr: iomuxc-gpr@20e0000 {
909 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
912 mux: mux-controller {
913 compatible = "mmio-mux";
914 #mux-control-cells = <1>;
919 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
934 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
939 clock-names = "ipg", "ahb";
940 #dma-cells = <3>;
941 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
946 compatible = "fsl,aips-bus", "simple-bus";
947 #address-cells = <1>;
948 #size-cells = <1>;
953 compatible = "fsl,sec-v4.0";
954 #address-cells = <1>;
955 #size-cells = <1>;
962 clock-names = "mem", "aclk", "ipg", "emi_slow";
965 compatible = "fsl,sec-v4.0-job-ring";
971 compatible = "fsl,sec-v4.0-job-ring";
982 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
988 ahb-burst-config = <0x0>;
989 tx-burst-size-dword = <0x10>;
990 rx-burst-size-dword = <0x10>;
995 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1002 ahb-burst-config = <0x0>;
1003 tx-burst-size-dword = <0x10>;
1004 rx-burst-size-dword = <0x10>;
1009 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1017 ahb-burst-config = <0x0>;
1018 tx-burst-size-dword = <0x10>;
1019 rx-burst-size-dword = <0x10>;
1024 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1032 ahb-burst-config = <0x0>;
1033 tx-burst-size-dword = <0x10>;
1034 rx-burst-size-dword = <0x10>;
1039 #index-cells = <1>;
1040 compatible = "fsl,imx6q-usbmisc";
1046 compatible = "fsl,imx6q-fec";
1048 interrupt-names = "int0", "pps";
1055 clock-names = "ipg", "ahb", "ptp", "enet_out";
1056 fsl,stop-mode = <&gpr 0x34 27>;
1068 compatible = "fsl,imx6q-usdhc";
1074 clock-names = "ipg", "ahb", "per";
1075 bus-width = <4>;
1080 compatible = "fsl,imx6q-usdhc";
1086 clock-names = "ipg", "ahb", "per";
1087 bus-width = <4>;
1092 compatible = "fsl,imx6q-usdhc";
1098 clock-names = "ipg", "ahb", "per";
1099 bus-width = <4>;
1104 compatible = "fsl,imx6q-usdhc";
1110 clock-names = "ipg", "ahb", "per";
1111 bus-width = <4>;
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1149 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1150 compatible = "fsl,imx6q-mmdc";
1155 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1156 compatible = "fsl,imx6q-mmdc";
1162 #address-cells = <2>;
1163 #size-cells = <1>;
1164 compatible = "fsl,imx6q-weim";
1168 fsl,weim-cs-gpr = <&gpr>;
1173 compatible = "fsl,imx6q-ocotp", "syscon";
1176 #address-cells = <1>;
1177 #size-cells = <1>;
1179 cpu_speed_grade: speed-grade@10 {
1187 tempmon_temp_grade: temp-grade@20 {
1203 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1209 compatible = "fsl,imx6-mipi-csi2";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1217 clock-names = "dphy", "ref", "pix";
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1233 remote-endpoint = <&ipu1_di0_mipi>;
1241 remote-endpoint = <&ipu1_di1_mipi>;
1248 compatible = "fsl,imx6q-vdoa";
1255 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1260 clock-names = "ipg", "per";
1262 dma-names = "rx", "tx";
1267 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1272 clock-names = "ipg", "per";
1274 dma-names = "rx", "tx";
1279 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1284 clock-names = "ipg", "per";
1286 dma-names = "rx", "tx";
1291 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1296 clock-names = "ipg", "per";
1298 dma-names = "rx", "tx";
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1306 compatible = "fsl,imx6q-ipu";
1313 clock-names = "bus", "di0", "di1";
1320 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1329 #address-cells = <1>;
1330 #size-cells = <0>;
1339 remote-endpoint = <&hdmi_mux_0>;
1344 remote-endpoint = <&mipi_mux_0>;
1349 remote-endpoint = <&lvds0_mux_0>;
1354 remote-endpoint = <&lvds1_mux_0>;
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1369 remote-endpoint = <&hdmi_mux_1>;
1374 remote-endpoint = <&mipi_mux_1>;
1379 remote-endpoint = <&lvds0_mux_1>;
1384 remote-endpoint = <&lvds1_mux_1>;