Lines Matching +full:0 +full:x021b0000
59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
108 #size-cells = <0>;
112 port@0 {
113 reg = <0>;
133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
138 #phy-cells = <0>;
143 #phy-cells = <0>;
155 reg = <0x00110000 0x2000>;
156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
157 <0 13 IRQ_TYPE_LEVEL_HIGH>,
158 <0 13 IRQ_TYPE_LEVEL_HIGH>,
159 <0 13 IRQ_TYPE_LEVEL_HIGH>;
168 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
170 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
179 dmas = <&dma_apbh 0>;
185 reg = <0x00120000 0x9000>;
186 interrupts = <0 115 0x04>;
195 #size-cells = <0>;
197 port@0 {
198 reg = <0>;
217 reg = <0x00130000 0x4000>;
218 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
229 reg = <0x00134000 0x4000>;
230 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
240 reg = <0x00a00600 0x20>;
241 interrupts = <1 13 0xf01>;
250 reg = <0x00a01000 0x1000>,
251 <0x00a00100 0x100>;
257 reg = <0x00a02000 0x1000>;
258 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
268 reg = <0x01ffc000 0x04000>,
269 <0x01f00000 0x80000>;
274 bus-range = <0x00 0xff>;
275 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
276 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
282 interrupt-map-mask = <0 0 0 0x7>;
283 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
284 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
285 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
286 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
298 reg = <0x02000000 0x100000>;
305 reg = <0x02000000 0x40000>;
310 reg = <0x02004000 0x4000>;
311 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
312 dmas = <&sdma 14 18 0>,
313 <&sdma 15 18 0>;
330 #size-cells = <0>;
332 reg = <0x02008000 0x4000>;
333 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
344 #size-cells = <0>;
346 reg = <0x0200c000 0x4000>;
347 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
358 #size-cells = <0>;
360 reg = <0x02010000 0x4000>;
361 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
372 #size-cells = <0>;
374 reg = <0x02014000 0x4000>;
375 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
386 reg = <0x02020000 0x4000>;
387 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
391 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
397 #sound-dai-cells = <0>;
399 reg = <0x02024000 0x4000>;
400 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
407 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
413 #sound-dai-cells = <0>;
416 reg = <0x02028000 0x4000>;
417 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
421 dmas = <&sdma 37 1 0>,
422 <&sdma 38 1 0>;
429 #sound-dai-cells = <0>;
432 reg = <0x0202c000 0x4000>;
433 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
437 dmas = <&sdma 41 1 0>,
438 <&sdma 42 1 0>;
445 #sound-dai-cells = <0>;
448 reg = <0x02030000 0x4000>;
449 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
453 dmas = <&sdma 45 1 0>,
454 <&sdma 46 1 0>;
462 reg = <0x02034000 0x4000>;
463 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
465 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
466 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
467 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
468 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
469 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
486 reg = <0x0203c000 0x4000>;
492 reg = <0x02040000 0x3c000>;
493 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
494 <0 3 IRQ_TYPE_LEVEL_HIGH>;
505 reg = <0x0207c000 0x4000>;
511 reg = <0x02080000 0x4000>;
512 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
522 reg = <0x02084000 0x4000>;
523 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
533 reg = <0x02088000 0x4000>;
534 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
544 reg = <0x0208c000 0x4000>;
545 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
554 reg = <0x02090000 0x4000>;
555 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
559 fsl,stop-mode = <&gpr 0x34 28>;
565 reg = <0x02094000 0x4000>;
566 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
570 fsl,stop-mode = <&gpr 0x34 29>;
576 reg = <0x02098000 0x4000>;
577 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
586 reg = <0x0209c000 0x4000>;
587 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
588 <0 67 IRQ_TYPE_LEVEL_HIGH>;
597 reg = <0x020a0000 0x4000>;
598 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
599 <0 69 IRQ_TYPE_LEVEL_HIGH>;
608 reg = <0x020a4000 0x4000>;
609 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
610 <0 71 IRQ_TYPE_LEVEL_HIGH>;
619 reg = <0x020a8000 0x4000>;
620 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
621 <0 73 IRQ_TYPE_LEVEL_HIGH>;
630 reg = <0x020ac000 0x4000>;
631 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
632 <0 75 IRQ_TYPE_LEVEL_HIGH>;
641 reg = <0x020b0000 0x4000>;
642 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
643 <0 77 IRQ_TYPE_LEVEL_HIGH>;
652 reg = <0x020b4000 0x4000>;
653 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
654 <0 79 IRQ_TYPE_LEVEL_HIGH>;
663 reg = <0x020b8000 0x4000>;
664 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
671 reg = <0x020bc000 0x4000>;
672 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
678 reg = <0x020c0000 0x4000>;
679 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
686 reg = <0x020c4000 0x4000>;
687 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
688 <0 88 IRQ_TYPE_LEVEL_HIGH>;
694 reg = <0x020c8000 0x1000>;
695 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
696 <0 54 IRQ_TYPE_LEVEL_HIGH>,
697 <0 127 IRQ_TYPE_LEVEL_HIGH>;
705 anatop-reg-offset = <0x110>;
711 anatop-enable-bit = <0>;
720 anatop-reg-offset = <0x120>;
723 anatop-min-bit-val = <0>;
726 anatop-enable-bit = <0>;
735 anatop-reg-offset = <0x130>;
738 anatop-min-bit-val = <0>;
741 anatop-enable-bit = <0>;
750 anatop-reg-offset = <0x140>;
751 anatop-vol-bit-shift = <0>;
753 anatop-delay-reg-offset = <0x170>;
767 anatop-reg-offset = <0x140>;
770 anatop-delay-reg-offset = <0x170>;
784 anatop-reg-offset = <0x140>;
787 anatop-delay-reg-offset = <0x170>;
798 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
803 #thermal-sensor-cells = <0>;
809 reg = <0x020c9000 0x1000>;
810 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
817 reg = <0x020ca000 0x1000>;
818 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
824 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
825 reg = <0x020cc000 0x4000>;
828 compatible = "fsl,sec-v4.0-mon-rtc-lp";
830 offset = <0x34>;
831 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
832 <0 20 IRQ_TYPE_LEVEL_HIGH>;
838 offset = <0x38>;
839 value = <0x60>;
840 mask = <0x60>;
845 compatible = "fsl,sec-v4.0-pwrkey";
859 reg = <0x020d0000 0x4000>;
860 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
864 reg = <0x020d4000 0x4000>;
865 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
870 reg = <0x020d8000 0x4000>;
871 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
872 <0 96 IRQ_TYPE_LEVEL_HIGH>;
878 reg = <0x020dc000 0x4000>;
881 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
888 #size-cells = <0>;
890 power-domain@0 {
891 reg = <0>;
892 #power-domain-cells = <0>;
896 #power-domain-cells = <0>;
910 reg = <0x20e0000 0x38>;
920 reg = <0x20e0000 0x4000>;
924 reg = <0x020e4000 0x4000>;
925 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
929 reg = <0x020e8000 0x4000>;
930 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
935 reg = <0x020ec000 0x4000>;
936 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
949 reg = <0x02100000 0x100000>;
953 compatible = "fsl,sec-v4.0";
956 reg = <0x2100000 0x10000>;
957 ranges = <0 0x2100000 0x10000>;
965 compatible = "fsl,sec-v4.0-job-ring";
966 reg = <0x1000 0x1000>;
971 compatible = "fsl,sec-v4.0-job-ring";
972 reg = <0x2000 0x1000>;
978 reg = <0x0217c000 0x4000>;
983 reg = <0x02184000 0x200>;
984 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
987 fsl,usbmisc = <&usbmisc 0>;
988 ahb-burst-config = <0x0>;
989 tx-burst-size-dword = <0x10>;
990 rx-burst-size-dword = <0x10>;
996 reg = <0x02184200 0x200>;
997 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
1002 ahb-burst-config = <0x0>;
1003 tx-burst-size-dword = <0x10>;
1004 rx-burst-size-dword = <0x10>;
1010 reg = <0x02184400 0x200>;
1011 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1017 ahb-burst-config = <0x0>;
1018 tx-burst-size-dword = <0x10>;
1019 rx-burst-size-dword = <0x10>;
1025 reg = <0x02184600 0x200>;
1026 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1032 ahb-burst-config = <0x0>;
1033 tx-burst-size-dword = <0x10>;
1034 rx-burst-size-dword = <0x10>;
1041 reg = <0x02184800 0x200>;
1047 reg = <0x02188000 0x4000>;
1049 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1050 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1056 fsl,stop-mode = <&gpr 0x34 27>;
1061 reg = <0x0218c000 0x4000>;
1062 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1064 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1069 reg = <0x02190000 0x4000>;
1070 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1081 reg = <0x02194000 0x4000>;
1082 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1093 reg = <0x02198000 0x4000>;
1094 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1105 reg = <0x0219c000 0x4000>;
1106 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1117 #size-cells = <0>;
1119 reg = <0x021a0000 0x4000>;
1120 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1127 #size-cells = <0>;
1129 reg = <0x021a4000 0x4000>;
1130 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1137 #size-cells = <0>;
1139 reg = <0x021a8000 0x4000>;
1140 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1146 reg = <0x021ac000 0x4000>;
1151 reg = <0x021b0000 0x4000>;
1157 reg = <0x021b4000 0x4000>;
1165 reg = <0x021b8000 0x4000>;
1166 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1174 reg = <0x021bc000 0x4000>;
1180 reg = <0x10 4>;
1184 reg = <0x38 4>;
1188 reg = <0x20 4>;
1193 reg = <0x021d0000 0x4000>;
1194 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1198 reg = <0x021d4000 0x4000>;
1199 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1204 reg = <0x021d8000 0x4000>;
1210 reg = <0x021dc000 0x4000>;
1212 #size-cells = <0>;
1213 interrupts = <0 100 0x04>, <0 101 0x04>;
1222 reg = <0x021e0000 0x4000>;
1227 #size-cells = <0>;
1229 port@0 {
1230 reg = <0>;
1249 reg = <0x021e4000 0x4000>;
1250 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1256 reg = <0x021e8000 0x4000>;
1257 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1261 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1268 reg = <0x021ec000 0x4000>;
1269 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1273 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1280 reg = <0x021f0000 0x4000>;
1281 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1285 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1292 reg = <0x021f4000 0x4000>;
1293 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1297 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1305 #size-cells = <0>;
1307 reg = <0x02400000 0x400000>;
1308 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1309 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1316 ipu1_csi0: port@0 {
1317 reg = <0>;
1330 #size-cells = <0>;
1333 ipu1_di0_disp0: endpoint@0 {
1334 reg = <0>;
1360 #size-cells = <0>;
1363 ipu1_di1_disp1: endpoint@0 {
1364 reg = <0>;