Lines Matching +full:0 +full:x38
15 #clock-cells = <0>;
21 brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
25 pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
31 #size-cells = <0>;
34 pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
38 port@0 {
39 reg = <0>;
56 #size-cells = <0>;
59 button-0 {
63 pinctrl-0 = <&pinctrl_dhcom_a>;
72 pinctrl-0 = <&pinctrl_dhcom_b>;
81 pinctrl-0 = <&pinctrl_dhcom_c>;
90 pinctrl-0 = <&pinctrl_dhcom_d>;
108 pinctrl-0 = <&pinctrl_dhcom_e>;
118 pinctrl-0 = <&pinctrl_dhcom_f>;
127 pinctrl-0 = <&pinctrl_dhcom_h>;
136 pinctrl-0 = <&pinctrl_dhcom_i>;
168 pinctrl-0 = <&pinctrl_audmux_ext>;
186 pinctrl-0 = <&pinctrl_enet_1G>;
192 #size-cells = <0>;
197 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
198 pinctrl-0 = <&pinctrl_ethphy7>;
205 rxd0-skew-ps = <0>;
206 rxd1-skew-ps = <0>;
207 rxd2-skew-ps = <0>;
208 rxd3-skew-ps = <0>;
209 rxdv-skew-ps = <0>;
211 txd0-skew-ps = <0>;
212 txd1-skew-ps = <0>;
213 txd2-skew-ps = <0>;
214 txd3-skew-ps = <0>;
215 txen-skew-ps = <0>;
227 #sound-dai-cells = <0>;
230 reg = <0x0a>;
239 pinctrl-0 = <&pinctrl_dhcom_e>;
241 reg = <0x38>;
250 pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
268 pinctrl-0 = <
294 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
295 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
296 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
297 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
303 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
304 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
305 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
306 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
307 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
308 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
309 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
310 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
311 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
312 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
313 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
314 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
315 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
316 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
317 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
323 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */
324 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */
325 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */
331 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
332 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
333 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
334 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
335 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
336 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
337 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
338 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
339 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
340 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
341 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
342 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
343 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
344 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
345 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
346 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
347 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
348 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
349 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
350 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
351 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
352 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
353 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
354 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
355 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
356 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
357 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
358 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38