Lines Matching +full:mux +full:- +full:reg +full:- +full:masks
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
40 clock-latency = <61036>; /* two CLK32 periods */
41 #cooling-cells = <2>;
47 clock-names = "arm", "pll2_pfd2_396m", "step",
49 arm-supply = <®_arm>;
50 pu-supply = <®_pu>;
51 soc-supply = <®_soc>;
52 nvmem-cells = <&cpu_speed_grade>;
53 nvmem-cell-names = "speed_grade";
57 compatible = "arm,cortex-a9";
59 reg = <1>;
60 next-level-cache = <&L2>;
61 operating-points = <
69 fsl,soc-operating-points = <
70 /* ARM kHz SOC-PU uV */
77 clock-latency = <61036>; /* two CLK32 periods */
78 #cooling-cells = <2>;
84 clock-names = "arm", "pll2_pfd2_396m", "step",
86 arm-supply = <®_arm>;
87 pu-supply = <®_pu>;
88 soc-supply = <®_soc>;
92 compatible = "arm,cortex-a9";
94 reg = <2>;
95 next-level-cache = <&L2>;
96 operating-points = <
104 fsl,soc-operating-points = <
105 /* ARM kHz SOC-PU uV */
112 clock-latency = <61036>; /* two CLK32 periods */
113 #cooling-cells = <2>;
119 clock-names = "arm", "pll2_pfd2_396m", "step",
121 arm-supply = <®_arm>;
122 pu-supply = <®_pu>;
123 soc-supply = <®_soc>;
127 compatible = "arm,cortex-a9";
129 reg = <3>;
130 next-level-cache = <&L2>;
131 operating-points = <
139 fsl,soc-operating-points = <
140 /* ARM kHz SOC-PU uV */
147 clock-latency = <61036>; /* two CLK32 periods */
148 #cooling-cells = <2>;
154 clock-names = "arm", "pll2_pfd2_396m", "step",
156 arm-supply = <®_arm>;
157 pu-supply = <®_pu>;
158 soc-supply = <®_soc>;
164 compatible = "mmio-sram";
165 reg = <0x00900000 0x40000>;
170 spba-bus@2000000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
175 reg = <0x02018000 0x4000>;
179 clock-names = "ipg", "per";
181 dma-names = "rx", "tx";
188 compatible = "fsl,imx6q-ahci";
189 reg = <0x02200000 0x4000>;
194 clock-names = "sata", "sata_ref", "ahb";
200 reg = <0x02204000 0x4000>;
204 clock-names = "bus", "core";
205 power-domains = <&pd_pu>;
206 #cooling-cells = <2>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 compatible = "fsl,imx6q-ipu";
213 reg = <0x02800000 0x400000>;
219 clock-names = "bus", "di0", "di1";
223 reg = <0>;
226 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
231 reg = <1>;
234 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 reg = <2>;
244 reg = <0>;
248 reg = <1>;
249 remote-endpoint = <&hdmi_mux_2>;
253 reg = <2>;
254 remote-endpoint = <&mipi_mux_2>;
258 reg = <3>;
259 remote-endpoint = <&lvds0_mux_2>;
263 reg = <4>;
264 remote-endpoint = <&lvds1_mux_2>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 reg = <3>;
274 reg = <1>;
275 remote-endpoint = <&hdmi_mux_3>;
279 reg = <2>;
280 remote-endpoint = <&mipi_mux_3>;
284 reg = <3>;
285 remote-endpoint = <&lvds0_mux_3>;
289 reg = <4>;
290 remote-endpoint = <&lvds1_mux_3>;
296 capture-subsystem {
297 compatible = "fsl,imx-capture-subsystem";
301 display-subsystem {
302 compatible = "fsl,imx-display-subsystem";
308 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
317 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
322 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
326 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
330 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
335 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
341 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
346 compatible = "video-mux";
347 mux-controls = <&mux 0>;
348 #address-cells = <1>;
349 #size-cells = <0>;
352 reg = <0>;
355 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
360 reg = <1>;
367 reg = <2>;
370 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
376 compatible = "video-mux";
377 mux-controls = <&mux 1>;
378 #address-cells = <1>;
379 #size-cells = <0>;
382 reg = <0>;
385 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
390 reg = <1>;
397 reg = <2>;
400 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
407 compatible = "fsl,imx6q-hdmi";
411 reg = <2>;
414 remote-endpoint = <&ipu2_di0_hdmi>;
419 reg = <3>;
422 remote-endpoint = <&ipu2_di1_hdmi>;
429 compatible = "fsl,imx6q-iomuxc";
434 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
443 clock-names = "di0_pll", "di1_pll",
447 lvds-channel@0 {
449 reg = <2>;
452 remote-endpoint = <&ipu2_di0_lvds0>;
457 reg = <3>;
460 remote-endpoint = <&ipu2_di1_lvds0>;
465 lvds-channel@1 {
467 reg = <2>;
470 remote-endpoint = <&ipu2_di0_lvds1>;
475 reg = <3>;
478 remote-endpoint = <&ipu2_di1_lvds1>;
486 reg = <1>;
489 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
494 reg = <2>;
497 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
502 reg = <3>;
505 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
510 reg = <4>;
513 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
521 reg = <2>;
524 remote-endpoint = <&ipu2_di0_mipi>;
529 reg = <3>;
532 remote-endpoint = <&ipu2_di1_mipi>;
538 &mux {
539 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
549 compatible = "fsl,imx6q-vpu", "cnm,coda960";