Lines Matching +full:0 +full:x02200000
17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
165 reg = <0x00900000 0x40000>;
173 #size-cells = <0>;
175 reg = <0x02018000 0x4000>;
176 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
189 reg = <0x02200000 0x4000>;
190 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
200 reg = <0x02204000 0x4000>;
201 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
211 #size-cells = <0>;
213 reg = <0x02800000 0x400000>;
214 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
215 <0 7 IRQ_TYPE_LEVEL_HIGH>;
222 ipu2_csi0: port@0 {
223 reg = <0>;
240 #size-cells = <0>;
243 ipu2_di0_disp0: endpoint@0 {
244 reg = <0>;
270 #size-cells = <0>;
308 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
317 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
322 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
330 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
335 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
341 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
347 mux-controls = <&mux 0>;
349 #size-cells = <0>;
351 port@0 {
352 reg = <0>;
379 #size-cells = <0>;
381 port@0 {
382 reg = <0>;
447 lvds-channel@0 {
539 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
540 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
541 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
542 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
543 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
544 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
545 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */