Lines Matching +full:0 +full:x5000
16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
61 #size-cells = <0>;
70 panel: display@0 {
72 reg = <0>;
130 gpio-fan,speed-map = <0 0>, <10000 1>;
178 #size-cells = <0>;
182 reg = <0x26>;
203 #address-cells = <0>;
209 #size-cells = <0>;
211 port@0 {
212 reg = <0>;
253 #size-cells = <0>;
255 phy0: phy@0 {
256 reg = <0>;
258 interrupts = <0>;
295 pinctrl-0 = <&pflash_default_pins>;
299 reg = <0x30000000 0x02000000>;
309 partition@0 {
311 reg = <0x00000000 0x00040000>;
321 reg = <0x00040000 0x01f40000>;
327 reg = <0x01f80000 0x00040000>;
337 reg = <0x01fc0000 0x00020000>;
342 reg = <0x01fe0000 0x00020000>;
425 cortina,gemini-ata-muxmode = <0>;
432 pinctrl-0 = <&gpio0_default_pins>;
437 pinctrl-0 = <&gpio1_default_pins>;
442 interrupt-map-mask = <0xf800 0 0 7>;
444 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
445 <0x4800 0 0 2 &pci_intc 1>,
446 <0x4800 0 0 3 &pci_intc 2>,
447 <0x4800 0 0 4 &pci_intc 3>,
448 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
449 <0x5000 0 0 2 &pci_intc 2>,
450 <0x5000 0 0 3 &pci_intc 3>,
451 <0x5000 0 0 4 &pci_intc 0>,
452 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
453 <0x5800 0 0 2 &pci_intc 3>,
454 <0x5800 0 0 3 &pci_intc 0>,
455 <0x5800 0 0 4 &pci_intc 1>,
456 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
457 <0x6000 0 0 2 &pci_intc 0>,
458 <0x6000 0 0 3 &pci_intc 1>,
459 <0x6000 0 0 4 &pci_intc 2>;
465 ethernet-port@0 {
486 drive0: ide-port@0 {
487 reg = <0>;
488 #thermal-sensor-cells = <0>;