Lines Matching +full:clock +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
45 cluster_a15_opp_table: opp-table0 {
46 compatible = "operating-points-v2";
47 opp-shared;
49 opp-1800000000 {
50 opp-hz = /bits/ 64 <1800000000>;
51 opp-microvolt = <1250000 1250000 1500000>;
52 clock-latency-ns = <140000>;
54 opp-1700000000 {
55 opp-hz = /bits/ 64 <1700000000>;
56 opp-microvolt = <1212500 1212500 1500000>;
57 clock-latency-ns = <140000>;
59 opp-1600000000 {
60 opp-hz = /bits/ 64 <1600000000>;
61 opp-microvolt = <1175000 1175000 1500000>;
62 clock-latency-ns = <140000>;
64 opp-1500000000 {
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <1137500 1137500 1500000>;
67 clock-latency-ns = <140000>;
69 opp-1400000000 {
70 opp-hz = /bits/ 64 <1400000000>;
71 opp-microvolt = <1112500 1112500 1500000>;
72 clock-latency-ns = <140000>;
74 opp-1300000000 {
75 opp-hz = /bits/ 64 <1300000000>;
76 opp-microvolt = <1062500 1062500 1500000>;
77 clock-latency-ns = <140000>;
79 opp-1200000000 {
80 opp-hz = /bits/ 64 <1200000000>;
81 opp-microvolt = <1037500 1037500 1500000>;
82 clock-latency-ns = <140000>;
84 opp-1100000000 {
85 opp-hz = /bits/ 64 <1100000000>;
86 opp-microvolt = <1012500 1012500 1500000>;
87 clock-latency-ns = <140000>;
89 opp-1000000000 {
90 opp-hz = /bits/ 64 <1000000000>;
91 opp-microvolt = < 987500 987500 1500000>;
92 clock-latency-ns = <140000>;
94 opp-900000000 {
95 opp-hz = /bits/ 64 <900000000>;
96 opp-microvolt = < 962500 962500 1500000>;
97 clock-latency-ns = <140000>;
99 opp-800000000 {
100 opp-hz = /bits/ 64 <800000000>;
101 opp-microvolt = < 937500 937500 1500000>;
102 clock-latency-ns = <140000>;
104 opp-700000000 {
105 opp-hz = /bits/ 64 <700000000>;
106 opp-microvolt = < 912500 912500 1500000>;
107 clock-latency-ns = <140000>;
111 cluster_a7_opp_table: opp-table1 {
112 compatible = "operating-points-v2";
113 opp-shared;
115 opp-1300000000 {
116 opp-hz = /bits/ 64 <1300000000>;
117 opp-microvolt = <1275000>;
118 clock-latency-ns = <140000>;
120 opp-1200000000 {
121 opp-hz = /bits/ 64 <1200000000>;
122 opp-microvolt = <1212500>;
123 clock-latency-ns = <140000>;
125 opp-1100000000 {
126 opp-hz = /bits/ 64 <1100000000>;
127 opp-microvolt = <1162500>;
128 clock-latency-ns = <140000>;
130 opp-1000000000 {
131 opp-hz = /bits/ 64 <1000000000>;
132 opp-microvolt = <1112500>;
133 clock-latency-ns = <140000>;
135 opp-900000000 {
136 opp-hz = /bits/ 64 <900000000>;
137 opp-microvolt = <1062500>;
138 clock-latency-ns = <140000>;
140 opp-800000000 {
141 opp-hz = /bits/ 64 <800000000>;
142 opp-microvolt = <1025000>;
143 clock-latency-ns = <140000>;
145 opp-700000000 {
146 opp-hz = /bits/ 64 <700000000>;
147 opp-microvolt = <975000>;
148 clock-latency-ns = <140000>;
150 opp-600000000 {
151 opp-hz = /bits/ 64 <600000000>;
152 opp-microvolt = <937500>;
153 clock-latency-ns = <140000>;
159 compatible = "arm,cci-400";
160 #address-cells = <1>;
161 #size-cells = <1>;
165 cci_control0: slave-if@4000 {
166 compatible = "arm,cci-400-ctrl-if";
167 interface-type = "ace";
170 cci_control1: slave-if@5000 {
171 compatible = "arm,cci-400-ctrl-if";
172 interface-type = "ace";
177 clock: clock-controller@10010000 { label
178 compatible = "samsung,exynos5420-clock", "syscon";
180 #clock-cells = <1>;
183 clock_audss: audss-clock-controller@3810000 {
184 compatible = "samsung,exynos5420-audss-clock";
186 #clock-cells = <1>;
187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
189 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
190 power-domains = <&mau_pd>;
194 compatible = "samsung,mfc-v7";
197 clocks = <&clock CLK_MFC>;
198 clock-names = "mfc";
199 power-domains = <&mfc_pd>;
201 iommu-names = "left", "right";
205 compatible = "samsung,exynos5420-dw-mshc-smu";
207 #address-cells = <1>;
208 #size-cells = <0>;
210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
211 clock-names = "biu", "ciu";
212 fifo-depth = <0x40>;
217 compatible = "samsung,exynos5420-dw-mshc-smu";
219 #address-cells = <1>;
220 #size-cells = <0>;
222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
223 clock-names = "biu", "ciu";
224 fifo-depth = <0x40>;
229 compatible = "samsung,exynos5420-dw-mshc";
231 #address-cells = <1>;
232 #size-cells = <0>;
234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
235 clock-names = "biu", "ciu";
236 fifo-depth = <0x40>;
240 dmc: memory-controller@10c20000 {
241 compatible = "samsung,exynos5422-dmc";
243 clocks = <&clock CLK_FOUT_SPLL>,
244 <&clock CLK_MOUT_SCLK_SPLL>,
245 <&clock CLK_FF_DOUT_SPLL2>,
246 <&clock CLK_FOUT_BPLL>,
247 <&clock CLK_MOUT_BPLL>,
248 <&clock CLK_SCLK_BPLL>,
249 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
250 <&clock CLK_MOUT_MCLK_CDREX>;
251 clock-names = "fout_spll",
259 samsung,syscon-clk = <&clock>;
264 compatible = "samsung,exynos5420-nocp";
270 compatible = "samsung,exynos5420-nocp";
276 compatible = "samsung,exynos5420-nocp";
282 compatible = "samsung,exynos5420-nocp";
288 compatible = "samsung,exynos5420-nocp";
294 compatible = "samsung,exynos5420-nocp";
300 compatible = "samsung,exynos-ppmu";
302 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
303 clock-names = "ppmu";
305 ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
306 event-name = "ppmu-event3-dmc0_0";
312 compatible = "samsung,exynos-ppmu";
314 clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
315 clock-names = "ppmu";
317 ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
318 event-name = "ppmu-event3-dmc0_1";
324 compatible = "samsung,exynos-ppmu";
326 clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
327 clock-names = "ppmu";
329 ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
330 event-name = "ppmu-event3-dmc1_0";
336 compatible = "samsung,exynos-ppmu";
338 clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
339 clock-names = "ppmu";
341 ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
342 event-name = "ppmu-event3-dmc1_1";
347 gsc_pd: power-domain@10044000 {
348 compatible = "samsung,exynos4210-pd";
350 #power-domain-cells = <0>;
354 isp_pd: power-domain@10044020 {
355 compatible = "samsung,exynos4210-pd";
357 #power-domain-cells = <0>;
361 mfc_pd: power-domain@10044060 {
362 compatible = "samsung,exynos4210-pd";
364 #power-domain-cells = <0>;
368 g3d_pd: power-domain@10044080 {
369 compatible = "samsung,exynos4210-pd";
371 #power-domain-cells = <0>;
375 disp_pd: power-domain@100440c0 {
376 compatible = "samsung,exynos4210-pd";
378 #power-domain-cells = <0>;
382 mau_pd: power-domain@100440e0 {
383 compatible = "samsung,exynos4210-pd";
385 #power-domain-cells = <0>;
389 msc_pd: power-domain@10044120 {
390 compatible = "samsung,exynos4210-pd";
392 #power-domain-cells = <0>;
397 compatible = "samsung,exynos5420-pinctrl";
401 wakeup-interrupt-controller {
402 compatible = "samsung,exynos4210-wakeup-eint";
403 interrupt-parent = <&gic>;
409 compatible = "samsung,exynos5420-pinctrl";
415 compatible = "samsung,exynos5420-pinctrl";
421 compatible = "samsung,exynos5420-pinctrl";
427 compatible = "samsung,exynos5420-pinctrl";
430 power-domains = <&mau_pd>;
438 clock-names = "apb_pclk";
439 #dma-cells = <1>;
440 #dma-channels = <6>;
441 #dma-requests = <16>;
442 power-domains = <&mau_pd>;
449 clocks = <&clock CLK_PDMA0>;
450 clock-names = "apb_pclk";
451 #dma-cells = <1>;
452 #dma-channels = <8>;
453 #dma-requests = <32>;
460 clocks = <&clock CLK_PDMA1>;
461 clock-names = "apb_pclk";
462 #dma-cells = <1>;
463 #dma-channels = <8>;
464 #dma-requests = <32>;
471 clocks = <&clock CLK_MDMA0>;
472 clock-names = "apb_pclk";
473 #dma-cells = <1>;
474 #dma-channels = <8>;
475 #dma-requests = <1>;
482 clocks = <&clock CLK_MDMA1>;
483 clock-names = "apb_pclk";
484 #dma-cells = <1>;
485 #dma-channels = <8>;
486 #dma-requests = <1>;
488 * MDMA1 can support both secure and non-secure
498 compatible = "samsung,exynos5420-i2s";
503 dma-names = "tx", "rx", "tx-sec";
507 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
508 #clock-cells = <1>;
509 clock-output-names = "i2s_cdclk0";
510 #sound-dai-cells = <1>;
511 samsung,idma-addr = <0x03000000>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&i2s0_bus>;
514 power-domains = <&mau_pd>;
519 compatible = "samsung,exynos5420-i2s";
523 dma-names = "tx", "rx";
524 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
525 clock-names = "iis", "i2s_opclk0";
526 #clock-cells = <1>;
527 clock-output-names = "i2s_cdclk1";
528 #sound-dai-cells = <1>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2s1_bus>;
535 compatible = "samsung,exynos5420-i2s";
539 dma-names = "tx", "rx";
540 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
541 clock-names = "iis", "i2s_opclk0";
542 #clock-cells = <1>;
543 clock-output-names = "i2s_cdclk2";
544 #sound-dai-cells = <1>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&i2s2_bus>;
551 compatible = "samsung,exynos4210-spi";
556 dma-names = "tx", "rx";
557 #address-cells = <1>;
558 #size-cells = <0>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&spi0_bus>;
561 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
562 clock-names = "spi", "spi_busclk0";
567 compatible = "samsung,exynos4210-spi";
572 dma-names = "tx", "rx";
573 #address-cells = <1>;
574 #size-cells = <0>;
575 pinctrl-names = "default";
576 pinctrl-0 = <&spi1_bus>;
577 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
578 clock-names = "spi", "spi_busclk0";
583 compatible = "samsung,exynos4210-spi";
588 dma-names = "tx", "rx";
589 #address-cells = <1>;
590 #size-cells = <0>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&spi2_bus>;
593 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
594 clock-names = "spi", "spi_busclk0";
598 dp_phy: dp-video-phy {
599 compatible = "samsung,exynos5420-dp-video-phy";
600 samsung,pmu-syscon = <&pmu_system_controller>;
601 #phy-cells = <0>;
604 mipi_phy: mipi-video-phy {
605 compatible = "samsung,s5pv210-mipi-video-phy";
607 #phy-cells = <1>;
611 compatible = "samsung,exynos5410-mipi-dsi";
615 phy-names = "dsim";
616 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
617 clock-names = "bus_clk", "pll_clk";
618 #address-cells = <1>;
619 #size-cells = <0>;
624 compatible = "samsung,exynos5250-hsi2c";
627 #address-cells = <1>;
628 #size-cells = <0>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&i2c8_hs_bus>;
631 clocks = <&clock CLK_USI4>;
632 clock-names = "hsi2c";
637 compatible = "samsung,exynos5250-hsi2c";
640 #address-cells = <1>;
641 #size-cells = <0>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&i2c9_hs_bus>;
644 clocks = <&clock CLK_USI5>;
645 clock-names = "hsi2c";
650 compatible = "samsung,exynos5250-hsi2c";
653 #address-cells = <1>;
654 #size-cells = <0>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&i2c10_hs_bus>;
657 clocks = <&clock CLK_USI6>;
658 clock-names = "hsi2c";
663 compatible = "samsung,exynos5420-hdmi";
666 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
667 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
668 <&clock CLK_MOUT_HDMI>;
669 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
672 samsung,syscon-phandle = <&pmu_system_controller>;
674 power-domains = <&disp_pd>;
675 #sound-dai-cells = <0>;
683 compatible = "samsung,s5p-cec";
686 clocks = <&clock CLK_HDMI_CEC>;
687 clock-names = "hdmicec";
688 samsung,syscon-phandle = <&pmu_system_controller>;
689 hdmi-phandle = <&hdmi>;
690 pinctrl-names = "default";
691 pinctrl-0 = <&hdmi_cec>;
696 compatible = "samsung,exynos5420-mixer";
699 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
700 <&clock CLK_SCLK_HDMI>;
701 clock-names = "mixer", "hdmi", "sclk_hdmi";
702 power-domains = <&disp_pd>;
708 compatible = "samsung,exynos5250-rotator";
711 clocks = <&clock CLK_ROTATOR>;
712 clock-names = "rotator";
716 gsc_0: video-scaler@13e00000 {
717 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
720 clocks = <&clock CLK_GSCL0>;
721 clock-names = "gscl";
722 power-domains = <&gsc_pd>;
726 gsc_1: video-scaler@13e10000 {
727 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
730 clocks = <&clock CLK_GSCL1>;
731 clock-names = "gscl";
732 power-domains = <&gsc_pd>;
737 compatible = "samsung,exynos5420-mali", "arm,mali-t628";
742 interrupt-names = "job", "mmu", "gpu";
744 clocks = <&clock CLK_G3D>;
745 clock-names = "core";
746 power-domains = <&g3d_pd>;
747 operating-points-v2 = <&gpu_opp_table>;
750 #cooling-cells = <2>;
752 gpu_opp_table: opp-table {
753 compatible = "operating-points-v2";
755 opp-177000000 {
756 opp-hz = /bits/ 64 <177000000>;
757 opp-microvolt = <812500>;
759 opp-266000000 {
760 opp-hz = /bits/ 64 <266000000>;
761 opp-microvolt = <862500>;
763 opp-350000000 {
764 opp-hz = /bits/ 64 <350000000>;
765 opp-microvolt = <912500>;
767 opp-420000000 {
768 opp-hz = /bits/ 64 <420000000>;
769 opp-microvolt = <962500>;
771 opp-480000000 {
772 opp-hz = /bits/ 64 <480000000>;
773 opp-microvolt = <1000000>;
775 opp-543000000 {
776 opp-hz = /bits/ 64 <543000000>;
777 opp-microvolt = <1037500>;
779 opp-600000000 {
780 opp-hz = /bits/ 64 <600000000>;
781 opp-microvolt = <1150000>;
787 compatible = "samsung,exynos5420-scaler";
790 clocks = <&clock CLK_MSCL0>;
791 clock-names = "mscl";
792 power-domains = <&msc_pd>;
797 compatible = "samsung,exynos5420-scaler";
800 clocks = <&clock CLK_MSCL1>;
801 clock-names = "mscl";
802 power-domains = <&msc_pd>;
807 compatible = "samsung,exynos5420-scaler";
810 clocks = <&clock CLK_MSCL2>;
811 clock-names = "mscl";
812 power-domains = <&msc_pd>;
817 compatible = "samsung,exynos5420-jpeg";
820 clock-names = "jpeg";
821 clocks = <&clock CLK_JPEG>;
826 compatible = "samsung,exynos5420-jpeg";
829 clock-names = "jpeg";
830 clocks = <&clock CLK_JPEG2>;
834 pmu_system_controller: system-controller@10040000 {
835 compatible = "samsung,exynos5420-pmu", "syscon";
837 clock-names = "clkout16";
838 clocks = <&clock CLK_FIN_PLL>;
839 #clock-cells = <1>;
840 interrupt-controller;
841 #interrupt-cells = <3>;
842 interrupt-parent = <&gic>;
846 compatible = "samsung,exynos5420-tmu";
849 clocks = <&clock CLK_TMU>;
850 clock-names = "tmu_apbif";
851 #thermal-sensor-cells = <0>;
855 compatible = "samsung,exynos5420-tmu";
858 clocks = <&clock CLK_TMU>;
859 clock-names = "tmu_apbif";
860 #thermal-sensor-cells = <0>;
864 compatible = "samsung,exynos5420-tmu-ext-triminfo";
867 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
868 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
869 #thermal-sensor-cells = <0>;
873 compatible = "samsung,exynos5420-tmu-ext-triminfo";
876 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
877 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
878 #thermal-sensor-cells = <0>;
882 compatible = "samsung,exynos5420-tmu-ext-triminfo";
885 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
886 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
887 #thermal-sensor-cells = <0>;
891 compatible = "samsung,exynos-sysmmu";
893 interrupt-parent = <&combiner>;
895 clock-names = "sysmmu", "master";
896 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
897 #iommu-cells = <0>;
901 compatible = "samsung,exynos-sysmmu";
903 interrupt-parent = <&combiner>;
905 clock-names = "sysmmu", "master";
906 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
907 #iommu-cells = <0>;
911 compatible = "samsung,exynos-sysmmu";
913 interrupt-parent = <&combiner>;
915 clock-names = "sysmmu", "master";
916 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
917 power-domains = <&disp_pd>;
918 #iommu-cells = <0>;
922 compatible = "samsung,exynos-sysmmu";
924 interrupt-parent = <&combiner>;
926 clock-names = "sysmmu", "master";
927 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
928 power-domains = <&gsc_pd>;
929 #iommu-cells = <0>;
933 compatible = "samsung,exynos-sysmmu";
935 interrupt-parent = <&combiner>;
937 clock-names = "sysmmu", "master";
938 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
939 power-domains = <&gsc_pd>;
940 #iommu-cells = <0>;
944 compatible = "samsung,exynos-sysmmu";
946 interrupt-parent = <&combiner>;
948 clock-names = "sysmmu", "master";
949 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
950 power-domains = <&msc_pd>;
951 #iommu-cells = <0>;
955 compatible = "samsung,exynos-sysmmu";
958 clock-names = "sysmmu", "master";
959 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
960 power-domains = <&msc_pd>;
961 #iommu-cells = <0>;
965 compatible = "samsung,exynos-sysmmu";
968 clock-names = "sysmmu", "master";
969 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
970 power-domains = <&msc_pd>;
971 #iommu-cells = <0>;
975 compatible = "samsung,exynos-sysmmu";
977 interrupt-parent = <&combiner>;
979 clock-names = "sysmmu", "master";
980 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
981 power-domains = <&msc_pd>;
982 #iommu-cells = <0>;
986 compatible = "samsung,exynos-sysmmu";
988 interrupt-parent = <&combiner>;
990 clock-names = "sysmmu", "master";
991 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
992 power-domains = <&msc_pd>;
993 #iommu-cells = <0>;
997 compatible = "samsung,exynos-sysmmu";
999 interrupt-parent = <&combiner>;
1001 clock-names = "sysmmu", "master";
1002 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1003 power-domains = <&msc_pd>;
1004 #iommu-cells = <0>;
1008 compatible = "samsung,exynos-sysmmu";
1010 interrupt-parent = <&combiner>;
1012 clock-names = "sysmmu", "master";
1013 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1014 #iommu-cells = <0>;
1018 compatible = "samsung,exynos-sysmmu";
1020 interrupt-parent = <&combiner>;
1022 clock-names = "sysmmu", "master";
1023 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1024 #iommu-cells = <0>;
1028 compatible = "samsung,exynos-sysmmu";
1031 clock-names = "sysmmu", "master";
1032 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1033 #iommu-cells = <0>;
1037 compatible = "samsung,exynos-sysmmu";
1039 interrupt-parent = <&combiner>;
1041 clock-names = "sysmmu", "master";
1042 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1043 power-domains = <&mfc_pd>;
1044 #iommu-cells = <0>;
1048 compatible = "samsung,exynos-sysmmu";
1050 interrupt-parent = <&combiner>;
1052 clock-names = "sysmmu", "master";
1053 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1054 power-domains = <&mfc_pd>;
1055 #iommu-cells = <0>;
1059 compatible = "samsung,exynos-sysmmu";
1061 interrupt-parent = <&combiner>;
1063 clock-names = "sysmmu", "master";
1064 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1065 power-domains = <&disp_pd>;
1066 #iommu-cells = <0>;
1070 compatible = "samsung,exynos-sysmmu";
1072 interrupt-parent = <&combiner>;
1074 clock-names = "sysmmu", "master";
1075 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1076 power-domains = <&disp_pd>;
1077 #iommu-cells = <0>;
1080 bus_wcore: bus-wcore {
1081 compatible = "samsung,exynos-bus";
1082 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
1083 clock-names = "bus";
1087 bus_noc: bus-noc {
1088 compatible = "samsung,exynos-bus";
1089 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1090 clock-names = "bus";
1094 bus_fsys_apb: bus-fsys-apb {
1095 compatible = "samsung,exynos-bus";
1096 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1097 clock-names = "bus";
1101 bus_fsys: bus-fsys {
1102 compatible = "samsung,exynos-bus";
1103 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1104 clock-names = "bus";
1108 bus_fsys2: bus-fsys2 {
1109 compatible = "samsung,exynos-bus";
1110 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1111 clock-names = "bus";
1115 bus_mfc: bus-mfc {
1116 compatible = "samsung,exynos-bus";
1117 clocks = <&clock CLK_DOUT_ACLK333>;
1118 clock-names = "bus";
1122 bus_gen: bus-gen {
1123 compatible = "samsung,exynos-bus";
1124 clocks = <&clock CLK_DOUT_ACLK266>;
1125 clock-names = "bus";
1129 bus_peri: bus-peri {
1130 compatible = "samsung,exynos-bus";
1131 clocks = <&clock CLK_DOUT_ACLK66>;
1132 clock-names = "bus";
1136 bus_g2d: bus-g2d {
1137 compatible = "samsung,exynos-bus";
1138 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1139 clock-names = "bus";
1143 bus_g2d_acp: bus-g2d-acp {
1144 compatible = "samsung,exynos-bus";
1145 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1146 clock-names = "bus";
1150 bus_jpeg: bus-jpeg {
1151 compatible = "samsung,exynos-bus";
1152 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1153 clock-names = "bus";
1157 bus_jpeg_apb: bus-jpeg-apb {
1158 compatible = "samsung,exynos-bus";
1159 clocks = <&clock CLK_DOUT_ACLK166>;
1160 clock-names = "bus";
1164 bus_disp1_fimd: bus-disp1-fimd {
1165 compatible = "samsung,exynos-bus";
1166 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1167 clock-names = "bus";
1171 bus_disp1: bus-disp1 {
1172 compatible = "samsung,exynos-bus";
1173 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1174 clock-names = "bus";
1178 bus_gscl_scaler: bus-gscl-scaler {
1179 compatible = "samsung,exynos-bus";
1180 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1181 clock-names = "bus";
1185 bus_mscl: bus-mscl {
1186 compatible = "samsung,exynos-bus";
1187 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1188 clock-names = "bus";
1193 thermal-zones {
1194 cpu0_thermal: cpu0-thermal {
1195 thermal-sensors = <&tmu_cpu0>;
1196 #include "exynos5420-trip-points.dtsi"
1198 cpu1_thermal: cpu1-thermal {
1199 thermal-sensors = <&tmu_cpu1>;
1200 #include "exynos5420-trip-points.dtsi"
1202 cpu2_thermal: cpu2-thermal {
1203 thermal-sensors = <&tmu_cpu2>;
1204 #include "exynos5420-trip-points.dtsi"
1206 cpu3_thermal: cpu3-thermal {
1207 thermal-sensors = <&tmu_cpu3>;
1208 #include "exynos5420-trip-points.dtsi"
1210 gpu_thermal: gpu-thermal {
1211 thermal-sensors = <&tmu_gpu>;
1212 #include "exynos5420-trip-points.dtsi"
1218 clocks = <&clock CLK_TSADC>;
1219 clock-names = "adc";
1220 samsung,syscon-phandle = <&pmu_system_controller>;
1224 clocks = <&clock CLK_DP1>;
1225 clock-names = "dp";
1227 phy-names = "dp";
1228 power-domains = <&disp_pd>;
1232 compatible = "samsung,exynos5420-fimd";
1233 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1234 clock-names = "sclk_fimd", "fimd";
1235 power-domains = <&disp_pd>;
1237 iommu-names = "m0", "m1";
1242 clocks = <&clock CLK_G2D>;
1243 clock-names = "fimg2d";
1248 clocks = <&clock CLK_I2C0>;
1249 clock-names = "i2c";
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&i2c0_bus>;
1255 clocks = <&clock CLK_I2C1>;
1256 clock-names = "i2c";
1257 pinctrl-names = "default";
1258 pinctrl-0 = <&i2c1_bus>;
1262 clocks = <&clock CLK_I2C2>;
1263 clock-names = "i2c";
1264 pinctrl-names = "default";
1265 pinctrl-0 = <&i2c2_bus>;
1269 clocks = <&clock CLK_I2C3>;
1270 clock-names = "i2c";
1271 pinctrl-names = "default";
1272 pinctrl-0 = <&i2c3_bus>;
1276 clocks = <&clock CLK_USI0>;
1277 clock-names = "hsi2c";
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&i2c4_hs_bus>;
1283 clocks = <&clock CLK_USI1>;
1284 clock-names = "hsi2c";
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&i2c5_hs_bus>;
1290 clocks = <&clock CLK_USI2>;
1291 clock-names = "hsi2c";
1292 pinctrl-names = "default";
1293 pinctrl-0 = <&i2c6_hs_bus>;
1297 clocks = <&clock CLK_USI3>;
1298 clock-names = "hsi2c";
1299 pinctrl-names = "default";
1300 pinctrl-0 = <&i2c7_hs_bus>;
1304 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1305 clock-names = "fin_pll", "mct";
1309 clocks = <&clock CLK_SSS>;
1310 clock-names = "secss";
1314 clocks = <&clock CLK_PWM>;
1315 clock-names = "timers";
1319 clocks = <&clock CLK_RTC>;
1320 clock-names = "rtc";
1321 interrupt-parent = <&pmu_system_controller>;
1326 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1327 clock-names = "uart", "clk_uart_baud0";
1329 dma-names = "rx", "tx";
1333 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1334 clock-names = "uart", "clk_uart_baud0";
1336 dma-names = "rx", "tx";
1340 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1341 clock-names = "uart", "clk_uart_baud0";
1343 dma-names = "rx", "tx";
1347 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1348 clock-names = "uart", "clk_uart_baud0";
1350 dma-names = "rx", "tx";
1354 clocks = <&clock CLK_SSS>;
1355 clock-names = "secss";
1359 clocks = <&clock CLK_SSS>;
1360 clock-names = "secss";
1364 clocks = <&clock CLK_USBD300>;
1365 clock-names = "usbdrd30";
1369 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1370 clock-names = "phy", "ref";
1371 samsung,pmu-syscon = <&pmu_system_controller>;
1375 clocks = <&clock CLK_USBD301>;
1376 clock-names = "usbdrd30";
1384 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1385 clock-names = "phy", "ref";
1386 samsung,pmu-syscon = <&pmu_system_controller>;
1390 clocks = <&clock CLK_USBH20>;
1391 clock-names = "usbhost";
1395 clocks = <&clock CLK_USBH20>;
1396 clock-names = "usbhost";
1400 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1401 clock-names = "phy", "ref";
1402 samsung,sysreg-phandle = <&sysreg_system_controller>;
1403 samsung,pmureg-phandle = <&pmu_system_controller>;
1407 clocks = <&clock CLK_WDT>;
1408 clock-names = "watchdog";
1409 samsung,syscon-phandle = <&pmu_system_controller>;
1412 #include "exynos5420-pinctrl.dtsi"
1413 #include "exynos-syscon-restart.dtsi"