Lines Matching +full:0 +full:x10023c80
51 #size-cells = <0>;
64 cpu0: cpu@0 {
67 reg = <0>;
111 xusbxti: clock-0 {
113 clock-frequency = <0>;
114 #clock-cells = <0>;
120 clock-frequency = <0>;
121 #clock-cells = <0>;
127 clock-frequency = <0>;
128 #clock-cells = <0>;
146 reg = <0x02020000 0x40000>;
149 ranges = <0 0x02020000 0x40000>;
151 smp-sram@0 {
153 reg = <0x0 0x1000>;
158 reg = <0x3f000 0x1000>;
164 reg = <0x10000000 0x100>;
169 reg = <0x10010000 0x400>;
174 reg = <0x10020000 0x4000>;
191 reg = <0x10023C00 0x20>;
192 #power-domain-cells = <0>;
198 reg = <0x10023C40 0x20>;
199 #power-domain-cells = <0>;
205 reg = <0x10023C60 0x20>;
206 #power-domain-cells = <0>;
212 reg = <0x10023C80 0x20>;
213 #power-domain-cells = <0>;
219 reg = <0x10023CA0 0x20>;
220 #power-domain-cells = <0>;
226 reg = <0x10030000 0x20000>;
236 reg = <0x105C0000 0x2000>;
242 reg = <0x10070000 0x100>;
251 reg = <0x100C0000 0x100>;
255 #thermal-sensor-cells = <0>;
263 reg = <0x10481000 0x1000>,
264 <0x10482000 0x2000>,
265 <0x10484000 0x2000>,
266 <0x10486000 0x2000>;
273 reg = <0x10050000 0x800>;
288 reg = <0x11000000 0x1000>;
299 reg = <0x11400000 0x1000>;
305 reg = <0x11830000 0x1000>;
311 assigned-clock-rates = <0>, <150000000>;
319 reg = <0x11a60000 0x1000>;
324 #iommu-cells = <0>;
329 reg = <0x11c00000 0x30000>;
344 reg = <0x11C80000 0x10000>;
346 samsung,phy-type = <0>;
353 #size-cells = <0>;
359 reg = <0x11e20000 0x1000>;
364 #iommu-cells = <0>;
369 reg = <0x12480000 0x20000>;
373 phys = <&exynos_usbphy 0>;
380 reg = <0x12510000 0x1000>;
384 fifo-depth = <0x80>;
386 #size-cells = <0>;
392 reg = <0x12520000 0x1000>;
396 fifo-depth = <0x80>;
398 #size-cells = <0>;
404 reg = <0x12530000 0x1000>;
408 fifo-depth = <0x80>;
410 #size-cells = <0>;
416 reg = <0x125B0000 0x100>;
426 reg = <0x12680000 0x1000>;
437 reg = <0x12690000 0x1000>;
448 reg = <0x126C0000 0x100>;
459 reg = <0x13000000 0x10000>;
492 reg = <0x13400000 0x10000>;
502 reg = <0x13620000 0x1000>;
507 #iommu-cells = <0>;
512 reg = <0x13800000 0x100>;
517 pinctrl-0 = <&uart0_data &uart0_fctl>;
523 reg = <0x13810000 0x100>;
528 pinctrl-0 = <&uart1_data>;
534 reg = <0x13820000 0x100>;
539 pinctrl-0 = <&uart2_data>;
545 #size-cells = <0>;
547 reg = <0x13860000 0x100>;
552 pinctrl-0 = <&i2c0_bus>;
558 #size-cells = <0>;
560 reg = <0x13870000 0x100>;
565 pinctrl-0 = <&i2c1_bus>;
571 #size-cells = <0>;
573 reg = <0x13880000 0x100>;
578 pinctrl-0 = <&i2c2_bus>;
584 #size-cells = <0>;
586 reg = <0x13890000 0x100>;
591 pinctrl-0 = <&i2c3_bus>;
597 #size-cells = <0>;
599 reg = <0x138A0000 0x100>;
604 pinctrl-0 = <&i2c4_bus>;
610 #size-cells = <0>;
612 reg = <0x138B0000 0x100>;
617 pinctrl-0 = <&i2c5_bus>;
623 #size-cells = <0>;
625 reg = <0x138C0000 0x100>;
630 pinctrl-0 = <&i2c6_bus>;
636 #size-cells = <0>;
638 reg = <0x138D0000 0x100>;
643 pinctrl-0 = <&i2c7_bus>;
649 reg = <0x13920000 0x100>;
654 #size-cells = <0>;
657 samsung,spi-src-clk = <0>;
659 pinctrl-0 = <&spi0_bus>;
665 reg = <0x13930000 0x100>;
670 #size-cells = <0>;
673 samsung,spi-src-clk = <0>;
675 pinctrl-0 = <&spi1_bus>;
681 reg = <0x13970000 0x100>;
687 pinctrl-0 = <&i2s2_bus>;
694 reg = <0x139D0000 0x1000>;
706 reg = <0x106a0000 0x2000>;
712 reg = <0x106b0000 0x2000>;
718 reg = <0x106c0000 0x2000>;
724 reg = <0x112a0000 0x2000>;
732 reg = <0x116a0000 0x2000>;
740 reg = <0x11ac0000 0x2000>;
748 reg = <0x11e40000 0x2000>;
756 reg = <0x12630000 0x2000>;
764 reg = <0x13220000 0x2000>;
772 reg = <0x13660000 0x2000>;