Lines Matching +full:0 +full:x81000000
22 #size-cells = <0>;
24 cpu0: cpu@0 {
28 reg = <0>;
34 marvell,tauros2-cache-features = <0>;
46 #size-cells = <0>;
51 pinctrl-0 = <&pmx_i2cmux_0>;
55 i2c0: i2c@0 {
56 reg = <0>;
58 #size-cells = <0>;
65 #size-cells = <0>;
73 #size-cells = <0>;
84 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
85 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
87 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
88 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
89 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
90 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
91 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
101 bus-range = <0x00 0xff>;
103 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
104 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
105 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
106 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
107 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
108 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
113 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
114 reg = <0x0800 0 0 0 0>;
116 marvell,pcie-port = <0>;
120 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
121 0x81000000 0 0 0x81000000 0x1 0 1 0>;
122 bus-range = <0x00 0xff>;
125 interrupt-map-mask = <0 0 0 0>;
126 interrupt-map = <0 0 0 0 &intc 16>;
132 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
133 reg = <0x1000 0 0 0 0>;
139 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
140 0x81000000 0 0 0x81000000 0x2 0 1 0>;
141 bus-range = <0x00 0xff>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &intc 18>;
153 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
154 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
155 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
156 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
161 #size-cells = <0>;
162 cell-index = <0>;
164 reg = <0x10600 0x28>;
165 clocks = <&core_clk 0>;
166 pinctrl-0 = <&pmx_spi0>;
173 reg = <0x11000 0x20>;
175 #size-cells = <0>;
178 clocks = <&core_clk 0>;
184 reg = <0x12000 0x100>;
187 clocks = <&core_clk 0>;
193 reg = <0x12100 0x100>;
196 clocks = <&core_clk 0>;
197 pinctrl-0 = <&pmx_uart1>;
204 reg = <0x12200 0x100>;
207 clocks = <&core_clk 0>;
213 reg = <0x12300 0x100>;
216 clocks = <&core_clk 0>;
223 #size-cells = <0>;
226 reg = <0x14600 0x28>;
227 clocks = <&core_clk 0>;
233 reg = <0x20000 0x80>, <0x800100 0x8>;
238 reg = <0x20000 0x110>;
245 reg = <0x20110 0x8>;
246 interrupts = <0>;
254 reg = <0x20200 0x10>, <0x20210 0x10>;
259 reg = <0x20300 0x20>;
262 clocks = <&core_clk 0>;
267 reg = <0x20300 0x28>, <0x20108 0x4>;
270 clocks = <&core_clk 0>;
275 reg = <0x30000 0x10000>;
280 marvell,crypto-sram-size = <0x800>;
286 reg = <0x50000 0x1000>;
288 clocks = <&gate_clk 0>;
294 reg = <0x51000 0x1000>;
302 reg = <0x60800 0x100
303 0x60a00 0x100>;
322 reg = <0x60900 0x100
323 0x60b00 0x100>;
342 reg = <0x90000 0x100>;
345 pinctrl-0 = <&pmx_sdio1>;
353 #size-cells = <0>;
354 reg = <0x72000 0x4000>;
359 ethernet-port@0 {
361 reg = <0>;
372 #size-cells = <0>;
373 reg = <0x72004 0x84>;
385 reg = <0x92000 0x100>;
388 pinctrl-0 = <&pmx_sdio0>;
395 reg = <0xa0000 0x2400>;
406 reg = <0xa2000 0x0334>;
409 #phy-cells = <0>;
415 reg = <0xb0000 0x2210>;
424 reg = <0xb4000 0x2210>;
433 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
434 ranges = <0x00000000 0x000d0000 0x8000
435 0x00008000 0x000d8000 0x8000>;
445 #power-domain-cells = <0>;
446 marvell,pmu_pwr_mask = <0x00000008>;
447 marvell,pmu_iso_mask = <0x00000001>;
452 #power-domain-cells = <0>;
453 marvell,pmu_pwr_mask = <0x00000004>;
454 marvell,pmu_iso_mask = <0x00000002>;
461 reg = <0x001c 0x0c>, <0x005c 0x08>;
466 reg = <0x0038 0x4>;
467 clocks = <&core_clk 0>;
473 reg = <0x0064 0x8>;
479 reg = <0x0200 0x14>,
480 <0x0440 0x04>;
483 pmx_gpio_0: pmx-gpio-0 {
705 pmx_i2cmux_0: pmx-i2cmux-0 {
723 reg = <0x0214 0x4>;
731 reg = <0x0400 0x20>;
743 reg = <0x0420 0x20>;
753 reg = <0x8500 0x20>;
761 reg = <0xe802c 0x14>;
768 reg = <0xe8400 0x0c>;
774 reg = <0x810000 0x1000>;
781 reg = <0x820000 0x1000>;
788 reg = <0xffffe000 0x800>;
800 reg = <0x840000 0x4000>;