Lines Matching +full:ethernet +full:- +full:phy +full:- +full:ieee802
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
26 vcc_sdhci0: regulator-vcc-sdhci0 {
27 compatible = "regulator-fixed";
28 regulator-name = "SDHCI0 Vcc";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
32 enable-active-high;
35 vccq_sdhci0: regulator-vccq-sdhci0 {
36 compatible = "regulator-gpio";
37 regulator-name = "SDHCI0 VccQ";
38 regulator-min-microvolt = <1800000>;
39 regulator-max-microvolt = <3300000>;
41 gpios-states = <1>;
46 vcc_sdhci1: regulator-vcc-sdhci1 {
47 compatible = "regulator-fixed";
48 regulator-name = "SDHCI1 Vcc";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
52 enable-active-high;
55 vccq_sdhci1: regulator-vccq-sdhci1 {
56 compatible = "regulator-gpio";
57 regulator-name = "SDHCI1 VccQ";
58 regulator-min-microvolt = <1800000>;
59 regulator-max-microvolt = <3300000>;
61 gpios-states = <1>;
70 ethphy0: ethernet-phy@0 {
71 compatible = "ethernet-phy-ieee802.3-c22";
79 ethphy1: ethernet-phy@0 {
80 compatible = "ethernet-phy-ieee802.3-c22";
88 ethphy2: ethernet-phy@0 {
89 compatible = "ethernet-phy-ieee802.3-c22";
97 ethphy3: ethernet-phy@0 {
98 compatible = "ethernet-phy-ieee802.3-c22";
106 phy-mode = "rgmii";
107 phy-handle = <ðphy0>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_rgmii1_default>;
117 phy-mode = "rgmii";
118 phy-handle = <ðphy1>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_rgmii2_default>;
127 phy-mode = "rgmii";
128 phy-handle = <ðphy2>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_rgmii3_default>;
137 phy-mode = "rgmii";
138 phy-handle = <ðphy3>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_rgmii4_default>;
149 non-removable;
150 bus-width = <4>;
151 max-frequency = <100000000>;
152 clk-phase-mmc-hs200 = <9>, <225>;
163 m25p,fast-read;
165 spi-max-frequency = <50000000>;
166 #include "openbmc-flash-layout-64.dtsi"
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_spi1_default>;
177 m25p,fast-read;
179 spi-max-frequency = <100000000>;
185 compatible = "snps,dw-apb-uart";
266 * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be
268 * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the
276 * AST2600-A2 EVB also supports toggling signal voltage for sdhci1.
277 * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3
278 * as power-switch-gpio.
282 bus-width = <4>;
283 max-frequency = <100000000>;
284 sdhci-drive-type = /bits/ 8 <3>;
285 sdhci-caps-mask = <0x7 0x0>;
286 sdhci,wp-inverted;
287 vmmc-supply = <&vcc_sdhci0>;
288 vqmmc-supply = <&vccq_sdhci0>;
289 clk-phase-sd-hs = <7>, <200>;
294 bus-width = <4>;
295 max-frequency = <100000000>;
296 sdhci-drive-type = /bits/ 8 <3>;
297 sdhci-caps-mask = <0x7 0x0>;
298 sdhci,wp-inverted;
299 vmmc-supply = <&vcc_sdhci1>;
300 vqmmc-supply = <&vccq_sdhci1>;
301 clk-phase-sd-hs = <7>, <200>;