Lines Matching +full:0 +full:x81000000
36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
89 clocks = <&coreclk 0>;
95 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
96 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
99 clocks = <&coreclk 0>;
105 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
106 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
109 clocks = <&coreclk 0>;
115 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
116 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
119 clocks = <&coreclk 0>;
125 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
126 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
129 clocks = <&coreclk 0>;
137 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
141 reg = <0x8000 0x1000>;
144 arm,double-linefill-incr = <0>;
145 arm,double-linefill-wrap = <0>;
146 arm,double-linefill = <0>;
152 reg = <0xc000 0x58>;
157 reg = <0xc600 0x20>;
165 #size-cells = <0>;
167 reg = <0xd000 0x1000>,
168 <0xc100 0x100>;
173 #size-cells = <0>;
175 reg = <0xc0054 0x4>;
182 reg = <0xf0000 0xa000>, /* Packet Processor regs */
183 <0xc0000 0x3060>, /* LMS regs */
184 <0xc4000 0x100>, /* eth0 regs */
185 <0xc5000 0x100>; /* eth1 regs */
192 port-id = <0>;
205 reg = <0x10300 0x20>;
212 reg = <0x10600 0x50>;
214 #size-cells = <0>;
215 cell-index = <0>;
217 clocks = <&coreclk 0>;
224 reg = <0x10680 0x50>;
226 #size-cells = <0>;
229 clocks = <&coreclk 0>;
235 reg = <0x11000 0x20>;
237 #size-cells = <0>;
239 clocks = <&coreclk 0>;
245 reg = <0x11100 0x20>;
247 #size-cells = <0>;
249 clocks = <&coreclk 0>;
255 reg = <0x12000 0x100>;
259 clocks = <&coreclk 0>;
265 reg = <0x12100 0x100>;
269 clocks = <&coreclk 0>;
275 reg = <0x18000 0x24>;
311 reg = <0x18100 0x40>;
325 reg = <0x18140 0x40>;
339 reg = <0x18180 0x40>;
350 reg = <0x18200 0x100>;
355 reg = <0x18220 0x4>;
356 clocks = <&coreclk 0>;
362 reg = <0x18400 0x4>;
368 reg = <0x20000 0x100>, <0x20180 0x20>;
373 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
383 reg = <0x20300 0x30>, <0x21040 0x30>;
390 clocks = <&coreclk 0>, <&refclk>;
396 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
397 clocks = <&coreclk 0>, <&refclk>;
403 reg = <0x20800 0x10>;
408 reg = <0x21010 0x1c>;
413 reg = <0x50000 0x500>;
423 reg = <0x54000 0x500>;
431 reg = <0x58000 0x20000>,<0x5b880 0x80>;
441 reg = <0x60800 0x100
442 0x60A00 0x100>;
461 reg = <0x60900 0x100
462 0x60b00 0x100>;
481 reg = <0x90000 0x10000>;
491 marvell,crypto-sram-size = <0x800>;
496 reg = <0xa0000 0x5000>;
499 clock-names = "0", "1";
505 reg = <0xd0000 0x54>;
507 #size-cells = <0>;
515 reg = <0xd4000 0x200>;
527 reg = <0xe8078 0x4>, <0xe807c 0x8>;
533 reg = <0xe8204 0x04>;
539 reg = <0xe8250 0xc>;
555 bus-range = <0x00 0xff>;
558 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
559 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
560 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
561 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
562 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
563 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
565 pcie0: pcie@1,0 {
567 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
568 reg = <0x0800 0 0 0 0>;
572 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
573 0x81000000 0 0 0x81000000 0x1 0 1 0>;
574 bus-range = <0x00 0xff>;
575 interrupt-map-mask = <0 0 0 0>;
576 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
577 marvell,pcie-port = <0>;
578 marvell,pcie-lane = <0>;
583 pcie1: pcie@2,0 {
585 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
586 reg = <0x1000 0 0 0 0>;
590 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
591 0x81000000 0 0 0x81000000 0x2 0 1 0>;
592 bus-range = <0x00 0xff>;
593 interrupt-map-mask = <0 0 0 0>;
594 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
595 marvell,pcie-port = <0>;
605 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
609 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
614 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
618 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;