Lines Matching +full:0 +full:x81000000

35 			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
47 			bus-range = <0x00 0xff>;
50 			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
53 				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
54 				0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
55 				0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
57 			pcie0: pcie@1,0 {
59 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
60 				reg = <0x0800 0 0 0 0>;
64                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
65                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
66 				bus-range = <0x00 0xff>;
67 				interrupt-map-mask = <0 0 0 0>;
68 				interrupt-map = <0 0 0 0 &mpic 58>;
69 				marvell,pcie-port = <0>;
70 				marvell,pcie-lane = <0>;
75 			pcie2: pcie@2,0 {
77 				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
78 				reg = <0x1000 0 0 0 0>;
82                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
83                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
84 				bus-range = <0x00 0xff>;
85 				interrupt-map-mask = <0 0 0 0>;
86 				interrupt-map = <0 0 0 0 &mpic 62>;
88 				marvell,pcie-lane = <0>;
97 				reg = <0x08000 0x1000>;
98 				cache-id-part = <0x100>;
107 				reg = <0x18100 0x40>, <0x181c0 0x08>;
116 				clocks = <&coreclk 0>;
122 				reg = <0x18140 0x40>, <0x181c8 0x08>;
131 				clocks = <&coreclk 0>;
137 				reg = <0x18180 0x40>;
149 				reg = <0x18200 0x100>;
154 				reg = <0x18220 0x4>;
155 				clocks = <&coreclk 0>;
161 				reg = <0x18230 0x08>;
167 				reg = <0x18300 0x4
168 					0x18304 0x4>;
173 				reg = <0x18330 0x4>;
178 				reg = <0x21000 0x8>;
184 				reg = <0x30000 0x4000>;
186 				clocks = <&gateclk 0>;
193 				reg = <0x60800 0x100
194 				       0x60A00 0x100>;
212 				reg = <0x60900 0x100
213 				       0x60b00 0x100>;
231 				reg = <0x90000 0x10000>;
237 				marvell,crypto-sram-size = <0x7e0>;
243 			reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
248 			ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
257 			idle-sram@0 {
258 				reg = <0x0 0x20>;
270 	pinctrl-0 = <&uart0_pins>;
275 	pinctrl-0 = <&uart1_pins>;
280 	reg = <0x11000 0x20>;
284 	reg = <0x11100 0x20>;
288 	reg = <0x20a00 0x1d0>, <0x21870 0x58>;
302 	clocks = <&coreclk 0>;
306 	clocks = <&coreclk 0>;
411 	pinctrl-0 = <&spi0_pins1>;
417 	pinctrl-0 = <&spi1_pins>;