Lines Matching full:r0
85 mov r0, \val
90 mov r0, \val
244 mov r0, #0x17 @ angel_SWIreason_EnterSVC
248 safe_svcmode_maskall r0
282 mov r0, pc
283 and r0, r0, #0xf8000000
315 add r4, r0, #TEXT_OFFSET
326 mov r0, pc
327 cmp r0, r4
328 ldrcc r0, .Lheadroom
329 addcc r0, r0, pc
330 cmpcc r4, r0
334 restart: adr r0, LC1
335 ldr sp, [r0]
336 ldr r6, [r0, #4]
337 add sp, sp, r0
338 add r6, r6, r0
402 mov r0, r8
412 cmp r0, #1
413 sub r0, r4, #TEXT_OFFSET
414 bic r0, r0, #1
415 add r0, r0, #0x100
491 mrs r0, spsr
492 and r0, r0, #MODE_MASK
493 cmp r0, #HYP_MODE
501 adr_l r0, __hyp_stub_vectors
502 sub r0, r0, r5
503 add r0, r0, r10
528 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
530 stmdb r9!, {r0 - r3, r10 - r12, lr}
536 mov r0, r9 @ start of relocated zImage
540 badr r0, restart
541 add r0, r0, r6
542 mov pc, r0
545 adr r0, LC0
546 ldmia r0, {r1, r2, r3, r11, r12}
547 sub r0, r0, r1 @ calculate the delta offset
551 * r0 = delta
562 orrs r1, r0, r5
565 add r11, r11, r0
566 add r12, r12, r0
574 add r2, r2, r0
575 add r3, r3, r0
582 add r1, r1, r0 @ This fixes up C references
603 addlo r1, r1, r0 @ table. This fixes up the
609 not_relocated: mov r0, #0
610 1: str r0, [r2], #4 @ clear bss
611 str r0, [r2], #4
612 str r0, [r2], #4
613 str r0, [r2], #4
633 mov r0, r4
641 mov r0, r4 @ start of inflated image
642 add r1, r1, r0 @ end of inflated image
647 mrs r0, spsr @ Get saved CPU boot mode
648 and r0, r0, #MODE_MASK
649 cmp r0, #HYP_MODE @ if not booted in HYP mode...
652 adr_l r0, __hyp_reentry_vectors
683 params: ldr r0, =0x10000100 @ params_phys for RPC
720 * r0, r1, r2, r3, r9, r10, r12 corrupted
733 mov r0, #0x3f @ 4G, the whole
734 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
735 mcr p15, 0, r0, c6, c7, 1
737 mov r0, #0x80 @ PR7
738 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
739 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
740 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
742 mov r0, #0xc000
743 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
744 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
746 mov r0, #0
747 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
748 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
749 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
750 mrc p15, 0, r0, c1, c0, 0 @ read control reg
752 orr r0, r0, #0x002d @ .... .... ..1. 11.1
753 orr r0, r0, #0x1000 @ ...1 .... .... ....
755 mcr p15, 0, r0, c1, c0, 0 @ write control reg
757 mov r0, #0
758 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
759 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
763 mov r0, #0x3f @ 4G, the whole
764 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
766 mov r0, #0x80 @ PR7
767 mcr p15, 0, r0, c2, c0, 0 @ cache on
768 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
770 mov r0, #0xc000
771 mcr p15, 0, r0, c5, c0, 0 @ access permission
773 mov r0, #0
774 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
779 mrc p15, 0, r0, c1, c0, 0 @ read control reg
781 orr r0, r0, #0x000d @ .... .... .... 11.1
783 mov r0, #0
784 mcr p15, 0, r0, c1, c0, 0 @ write control reg
787 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
803 mov r0, r3
804 mov r9, r0, lsr #18
815 str r1, [r0], #4 @ 1:1 mapping
817 teq r0, r2
830 add r0, r3, r2, lsl #2
831 str r1, [r0], #4
833 str r1, [r0]
840 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
841 bic r0, r0, #2 @ A (no unaligned access fault)
842 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
843 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
848 mov r0, #4 @ put dcache in WT mode
849 mcr p15, 7, r0, c15, c0, 0
857 mov r0, #0
858 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
859 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
860 mrc p15, 0, r0, c1, c0, 0 @ read control reg
861 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
862 orr r0, r0, #0x0030
863 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
865 mov r0, #0
866 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
878 mov r0, #0
879 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
881 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
883 mrc p15, 0, r0, c1, c0, 0 @ read control reg
884 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
885 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
886 orr r0, r0, #0x003c @ write buffer
887 bic r0, r0, #2 @ A (no unaligned access fault)
888 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
891 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
893 orrne r0, r0, #1 @ MMU enabled
901 mcr p15, 0, r0, c7, c5, 4 @ ISB
902 mcr p15, 0, r0, c1, c0, 0 @ load control register
903 mrc p15, 0, r0, c1, c0, 0 @ and read it back
904 mov r0, #0
905 mcr p15, 0, r0, c7, c5, 4 @ ISB
912 mov r0, #0
913 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
914 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
915 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
916 mrc p15, 0, r0, c1, c0, 0 @ read control reg
917 orr r0, r0, #0x1000 @ I-cache enable
919 mov r0, #0
920 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
926 orr r0, r0, #0x000d @ Write buffer, mmu
933 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
934 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
935 sub pc, lr, r0, lsr #32 @ properly flush pipeline
1154 * r0, r1, r2, r3, r9, r12 corrupted
1163 mrc p15, 0, r0, c1, c0
1164 bic r0, r0, #0x000d
1165 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1166 mov r0, #0
1167 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1168 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1169 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1173 mrc p15, 0, r0, c1, c0
1174 bic r0, r0, #0x000d
1175 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1176 mov r0, #0
1177 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1182 mrc p15, 0, r0, c1, c0
1183 bic r0, r0, #0x000d
1184 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1185 mov r0, #0
1186 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1187 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1192 mrc p15, 0, r0, c1, c0
1194 bic r0, r0, #0x0005
1196 bic r0, r0, #0x0004
1198 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1199 mov r0, #0
1201 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1203 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1204 mcr p15, 0, r0, c7, c10, 4 @ DSB
1205 mcr p15, 0, r0, c7, c5, 4 @ ISB
1212 * r0 = start address
1275 bic r0, r0, r2 @ round down start to line size
1278 0: cmp r0, r11 @ finished?
1280 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1281 add r0, r0, r1
1295 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1296 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1351 @ phex corrupts {r0, r1, r2, r3}
1356 movmi r0, r3
1358 and r2, r0, #15
1359 mov r0, r0, lsr #4
1366 @ puts corrupts {r0, r1, r2, r3}
1368 1: ldrb r2, [r0], #1
1378 teq r0, #0
1381 @ putc corrupts {r0, r1, r2, r3}
1383 mov r2, r0
1384 loadsp r3, r1, r0
1385 mov r0, #0
1388 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1389 memdump: mov r12, r0
1392 2: mov r0, r11, lsl #2
1393 add r0, r0, r12
1396 mov r0, #':'
1398 1: mov r0, #' '
1400 ldr r0, [r12, r11, lsl #2]
1403 and r0, r11, #7
1404 teq r0, #3
1405 moveq r0, #' '
1407 and r0, r11, #7
1409 teq r0, #7
1411 mov r0, #'\n'
1438 mov r0, #0 @ must be 0
1449 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1450 bic r0, r0, #0x5 @ disable MMU and caches
1451 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1456 mov r4, r0 @ preserve image base
1459 adr_l r0, call_cache_fn
1473 mrs r0, cpsr @ get the current mode
1474 msr spsr_cxsf, r0 @ record boot mode
1475 and r0, r0, #MODE_MASK @ are we running in HYP mode?
1476 cmp r0, #HYP_MODE
1493 adr r0, __hyp_reentry_vectors
1494 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1506 msr spsr_cxsf, r0 @ record boot mode
1511 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1512 tst r0, #0x1 @ MMU enabled?
1516 mov r0, r8 @ DT start
1520 adr r0, 0f @ switch to our stack
1521 ldr sp, [r0]
1522 add sp, sp, r0