Lines Matching +full:non +full:- +full:pc
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
20 AR_CLASS( .arch armv7-a )
21 M_CLASS( .arch armv7-m )
105 kputc #'-'
109 kputc #'-'
114 kputc #'-'
158 * in little-endian form.
212 AR_CLASS( sub pc, pc, #3 ) @ A/R: switch to Thumb2 mode
237 * Booting from Angel - need to enter SVC mode and disable
254 * be needed here - is there an Angel SWI call for this?
272 * different platforms - we have chosen 128MB to allow
282 mov r0, pc
322 * That means r4 < pc || r4 - 16k page directory > &_end.
326 mov r0, pc
329 addcc r0, r0, pc
347 * With ZBOOT_ROM the bss/stack is non relocatable,
363 * r10 = end of this image, including bss/stack/malloc space if non XIP
391 /* preserve 64-bit alignment */
441 /* preserve 64-bit alignment */
456 * r10 = end of this image, including bss/stack/malloc space if non XIP
458 * r4 - 16k page directory >= r10 -> OK
459 * r4 + image length <= address of wont_overwrite -> OK
478 * Bump to the next 256-byte boundary with the size of
482 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
528 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
530 stmdb r9!, {r0 - r3, r10 - r12, lr}
542 mov pc, r0
668 .size LC0, . - LC0
671 LC1: .word .L_user_stack_end - LC1 @ sp
672 .word _edata - LC1 @ r6
673 .size LC1, . - LC1
676 .word _end - restart + 16384 + 1024*1024
679 .long (input_data_end - 4) - .
684 mov pc, lr
690 * dcache_line_size - get the minimum D-cache line size from the CTR register
738 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
739 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
740 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
743 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
744 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
748 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
749 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
758 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
759 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
760 mov pc, lr
768 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
788 mov pc, lr
813 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
827 mov r2, pc
834 mov pc, lr
861 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
863 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
868 mov pc, r12
885 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
891 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
895 bic r6, r6, #1 << 31 @ 32-bit translation system
906 mov pc, r12
917 orr r0, r0, #0x1000 @ I-cache enable
921 mov pc, r12
928 mov r1, #-1
935 sub pc, lr, r0, lsr #32 @ properly flush pipeline
959 * On v7-M the processor id is located in the V7M_SCB_CPUID
961 * v7-M (if existant at all) we just return early here.
964 * use cp15 registers that are not implemented on v7-M.
974 ARM( addeq pc, r12, r3 ) @ call cache function
976 THUMB( moveq pc, r12 ) @ call cache function
982 * - CPU ID match
983 * - CPU ID mask
984 * - 'cache on' method instruction
985 * - 'cache off' method instruction
986 * - 'cache flush' method instruction
999 mov pc, lr
1001 mov pc, lr
1003 mov pc, lr
1008 mov pc, lr
1010 mov pc, lr
1012 mov pc, lr
1019 mov pc, lr
1034 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
1042 mov pc, lr
1044 mov pc, lr
1046 mov pc, lr
1130 mov pc, lr
1132 mov pc, lr
1134 mov pc, lr
1137 .size proc_types, . - proc_types
1140 * If you get a "non-constant expression in ".if" statement"
1145 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1168 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1169 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1170 mov pc, lr
1178 mov pc, lr
1189 mov pc, lr
1206 mov pc, lr
1227 movne pc, lr
1242 mov pc, lr
1246 movne pc, lr
1251 mov pc, lr
1260 mov pc, lr
1288 mov pc, lr
1292 movne pc, lr
1297 mov pc, lr
1301 movne pc, lr
1318 mov r1, pc
1331 mov pc, lr
1336 movne pc, lr
1339 mov pc, lr
1349 .size phexbuf, . - phexbuf
1370 moveq pc, lr
1380 mov pc, lr
1415 mov pc, r10
1441 ARM( mov pc, r4 ) @ call kernel
1467 @ 32-bit addressable DRAM mapped 1:1 using short descriptors.
1470 @ U-Boot might decide to enter the EFI stub in HYP mode
1528 0: .long .L_user_stack_end - .