Lines Matching full:c0
38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
145 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
149 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
699 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
738 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
739 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
740 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
743 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
744 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
750 mrc p15, 0, r0, c1, c0, 0 @ read control reg
755 mcr p15, 0, r0, c1, c0, 0 @ write control reg
767 mcr p15, 0, r0, c2, c0, 0 @ cache on
768 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
771 mcr p15, 0, r0, c5, c0, 0 @ access permission
774 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
779 mrc p15, 0, r0, c1, c0, 0 @ read control reg
784 mcr p15, 0, r0, c1, c0, 0 @ write control reg
787 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
840 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
843 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
849 mcr p15, 7, r0, c15, c0, 0
860 mrc p15, 0, r0, c1, c0, 0 @ read control reg
874 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
883 mrc p15, 0, r0, c1, c0, 0 @ read control reg
892 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
897 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
898 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
899 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
902 mcr p15, 0, r0, c1, c0, 0 @ load control register
903 mrc p15, 0, r0, c1, c0, 0 @ and read it back
916 mrc p15, 0, r0, c1, c0, 0 @ read control reg
929 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
930 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
933 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
934 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
956 mrc p15, 0, r9, c0, c0 @ get processor ID
1163 mrc p15, 0, r0, c1, c0
1165 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1173 mrc p15, 0, r0, c1, c0
1175 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1177 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1182 mrc p15, 0, r0, c1, c0
1184 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1192 mrc p15, 0, r0, c1, c0
1198 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1266 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1304 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1338 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1449 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1451 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1479 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
1492 mcr p15, 4, r1, c1, c0, 0
1494 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1511 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR