Lines Matching +full:0 +full:xff0f0000
15 #define OF_DT_MAGIC 0xd00dfeed
17 #define OF_DT_MAGIC 0xedfe0dd0
38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
69 mov \rb, #0x80000000 @ physical base address
71 add \rb, \rb, #0x00050000 @ Ser3
73 add \rb, \rb, #0x00010000 @ Ser1
102 kputc #'0'
106 kputc #'0'
111 kputc #'0'
115 kputc #'0'
131 kputc #'0'
136 kputc #'0'
145 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
149 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
150 ARM( .inst 0xf57ff06f @ v7+ isb )
221 .word 0x04030201 @ endianness flag
222 .word 0x45454545 @ another magic number to indicate
244 mov r0, #0x17 @ angel_SWIreason_EnterSVC
245 ARM( swi 0x123456 ) @ angel_SWI_ARM
246 THUMB( svc 0xab ) @ angel_SWI_THUMB
283 and r0, r0, #0xf8000000
354 mov r5, #0 @ init dtb size to 0
370 ldr lr, [r6, #0]
409 * pointed by r8. Try the typical 0x100 offset from start
415 add r0, r0, #0x100
555 * r5 = appended dtb size (0 if not present)
581 1: ldr r1, [r11, #0] @ relocate entries in the GOT
600 1: ldr r1, [r11, #0] @ relocate entries in the GOT
609 not_relocated: mov r0, #0
654 __HVC(0) @ otherwise bounce to hyp mode
683 params: ldr r0, =0x10000100 @ params_phys for RPC
699 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
702 and \tmp, \tmp, #0xf @ cache line size encoding
733 mov r0, #0x3f @ 4G, the whole
734 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
735 mcr p15, 0, r0, c6, c7, 1
737 mov r0, #0x80 @ PR7
738 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
739 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
740 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
742 mov r0, #0xc000
743 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
744 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
746 mov r0, #0
747 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
748 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
749 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
750 mrc p15, 0, r0, c1, c0, 0 @ read control reg
752 orr r0, r0, #0x002d @ .... .... ..1. 11.1
753 orr r0, r0, #0x1000 @ ...1 .... .... ....
755 mcr p15, 0, r0, c1, c0, 0 @ write control reg
757 mov r0, #0
758 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
759 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
763 mov r0, #0x3f @ 4G, the whole
764 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
766 mov r0, #0x80 @ PR7
767 mcr p15, 0, r0, c2, c0, 0 @ cache on
768 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
770 mov r0, #0xc000
771 mcr p15, 0, r0, c5, c0, 0 @ access permission
773 mov r0, #0
774 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
779 mrc p15, 0, r0, c1, c0, 0 @ read control reg
781 orr r0, r0, #0x000d @ .... .... .... 11.1
783 mov r0, #0
784 mcr p15, 0, r0, c1, c0, 0 @ write control reg
787 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
791 #define CB_BITS 0x08
793 #define CB_BITS 0x0c
797 bic r3, r3, #0xff @ Align the pointer
798 bic r3, r3, #0x3f00
806 add r10, r9, #0x10000000 @ a reasonable RAM size
807 mov r1, #0x12 @ XN|U + section mapping
812 bic r1, r1, #0x1c @ clear XN|U + C + B
813 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
825 orr r1, r6, #0x04 @ ensure B is set for this
840 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
843 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
849 mcr p15, 7, r0, c15, c0, 0
855 mov r6, #CB_BITS | 0x12 @ U
857 mov r0, #0
858 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
859 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
860 mrc p15, 0, r0, c1, c0, 0 @ read control reg
861 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
862 orr r0, r0, #0x0030
865 mov r0, #0
866 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
874 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
875 tst r11, #0xf @ VMSA
876 movne r6, #CB_BITS | 0x02 @ !XN
878 mov r0, #0
879 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
880 tst r11, #0xf @ VMSA
881 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
883 mrc p15, 0, r0, c1, c0, 0 @ read control reg
885 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
886 orr r0, r0, #0x003c @ write buffer
892 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
894 movne r1, #0xfffffffd @ domain 0 = client
896 bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
897 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
898 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
899 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
901 mcr p15, 0, r0, c7, c5, 4 @ ISB
902 mcr p15, 0, r0, c1, c0, 0 @ load control register
903 mrc p15, 0, r0, c1, c0, 0 @ and read it back
904 mov r0, #0
905 mcr p15, 0, r0, c7, c5, 4 @ ISB
910 mov r6, #CB_BITS | 0x12 @ U
912 mov r0, #0
913 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
914 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
915 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
916 mrc p15, 0, r0, c1, c0, 0 @ read control reg
917 orr r0, r0, #0x1000 @ I-cache enable
919 mov r0, #0
920 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
926 orr r0, r0, #0x000d @ Write buffer, mmu
929 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
930 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
933 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
934 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
956 mrc p15, 0, r9, c0, c0 @ get processor ID
970 1: ldr r1, [r12, #0] @ get value
988 * We match an entry using: ((real_id ^ match) & mask) == 0
997 .word 0x41000000 @ old ARM ID
998 .word 0xff00f000
1006 .word 0x41007000 @ ARM7/710
1007 .word 0xfff8fe00
1015 .word 0x41807200 @ ARM720T (writethrough)
1016 .word 0xffffff00
1022 .word 0x41007400 @ ARM74x
1023 .word 0xff00ff00
1028 .word 0x41009400 @ ARM94x
1029 .word 0xff00ff00
1034 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
1035 .word 0xff0ffff0
1040 .word 0x00007000 @ ARM7 IDs
1041 .word 0x0000f000
1051 .word 0x4401a100 @ sa110 / sa1100
1052 .word 0xffffffe0
1057 .word 0x6901b110 @ sa1110
1058 .word 0xfffffff0
1063 .word 0x56056900
1064 .word 0xffffff00 @ PXA9xx
1069 .word 0x56158000 @ PXA168
1070 .word 0xfffff000
1075 .word 0x56050000 @ Feroceon
1076 .word 0xff0f0000
1083 .long 0x41009260 @ Old Feroceon
1084 .long 0xff00fff0
1090 .word 0x66015261 @ FA526
1091 .word 0xff01fff1
1098 .word 0x00020000 @ ARMv4T
1099 .word 0x000f0000
1104 .word 0x00050000 @ ARMv5TE
1105 .word 0x000f0000
1110 .word 0x00060000 @ ARMv5TEJ
1111 .word 0x000f0000
1116 .word 0x0007b000 @ ARMv6
1117 .word 0x000ff000
1122 .word 0x000f0000 @ new CPU Id
1123 .word 0x000f0000
1128 .word 0 @ unrecognised type
1129 .word 0
1145 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1163 mrc p15, 0, r0, c1, c0
1164 bic r0, r0, #0x000d
1165 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1166 mov r0, #0
1167 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1168 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1169 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1173 mrc p15, 0, r0, c1, c0
1174 bic r0, r0, #0x000d
1175 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1176 mov r0, #0
1177 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1182 mrc p15, 0, r0, c1, c0
1183 bic r0, r0, #0x000d
1184 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1185 mov r0, #0
1186 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1187 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1192 mrc p15, 0, r0, c1, c0
1194 bic r0, r0, #0x0005
1196 bic r0, r0, #0x0004
1198 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1199 mov r0, #0
1201 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1203 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1204 mcr p15, 0, r0, c7, c10, 4 @ DSB
1205 mcr p15, 0, r0, c7, c5, 4 @ ISB
1229 mov r3, #0
1230 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1233 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1235 bcs 2b @ entries 63 to 0
1237 bcs 1b @ segments 7 to 0
1239 teq r2, #0
1240 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1241 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1247 mov r1, #0
1248 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1249 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1250 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1254 mov r1, #0
1256 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1257 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1258 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1259 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1266 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1267 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1268 mov r10, #0
1270 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1278 0: cmp r0, r11 @ finished?
1280 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1282 b 0b
1284 mcr p15, 0, r10, c7, c10, 4 @ DSB
1285 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1286 mcr p15, 0, r10, c7, c10, 4 @ DSB
1287 mcr p15, 0, r10, c7, c5, 4 @ ISB
1293 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
1295 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1296 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1304 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1328 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1329 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1330 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1337 mov r1, #0
1338 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1353 mov r2, #0
1362 add r2, r2, #'0'
1369 teq r2, #0
1372 mov r1, #0x00020000
1378 teq r0, #0
1385 mov r0, #0
1391 mov r11, #0
1438 mov r0, #0 @ must be 0
1449 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1450 bic r0, r0, #0x5 @ disable MMU and caches
1451 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1460 adr r1, 0f @ clean the region of code we
1479 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
1480 tst r1, #0x1 @ MMU enabled at HYP?
1492 mcr p15, 4, r1, c1, c0, 0
1494 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1511 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1512 tst r0, #0x1 @ MMU enabled?
1520 adr r0, 0f @ switch to our stack
1524 mov r5, #0 @ appended DTB size
1525 mov r7, #0xFFFFFFFF @ machine ID
1528 0: .long .L_user_stack_end - .