Lines Matching full:erratum

799 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
808 	  r1p* erratum. If a code sequence containing an ARM/Thumb
825 	  erratum. For very specific sequences of memory operations, it is
839 	  erratum. Any asynchronous access to the L2 cache may encounter a
852 	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
865 	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
880 	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
890 	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
892 	  As a consequence of this erratum, some TLB entries which should be
903 	  (r2p*) erratum. Under very rare conditions, a faulty
917 	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
927 	  r3p*) erratum. A speculative memory access may cause a page table walk
938 	  r2p0) erratum. The Store Buffer does not have any automatic draining
949 	  r0p2 erratum (possible cache data corruption with
960 	  This option enables the workaround for erratum 764369
975 	 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
986 	  option enables the Linux kernel workaround for this erratum
995 	  (up to r0p4) erratum. In certain rare sequences of code, the
997 	  workaround disables the loop buffer to avoid the erratum.
1018 	  (all revs) erratum. In very rare timing conditions, a sequence
1028 	  (all revs) erratum. Within rare timing constraints, executing a
1037 	  (all revs) erratum. Under very rare timing conditions, the CPU might
1045 	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1057 	  This is identical to Cortex-A12 erratum 852422.  It is a separate
1058 	  config option from the A12 erratum due to the way errata are checked
1065 	  This option enables the workaround for the 857272 Cortex-A17 erratum.
1066 	  This erratum is not known to be fixed in any A17 revision.
1067 	  This is identical to Cortex-A12 erratum 857271.  It is a separate
1068 	  config option from the A12 erratum due to the way errata are checked
1108 	  However, because of this erratum, an L2 set/way cache maintenance