Lines Matching +full:way +full:- +full:select
1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_KEEPINITRD
12 select ARCH_HAS_KCOV
13 select ARCH_HAS_MEMBARRIER_SYNC_CORE
14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
16 select ARCH_HAS_PHYS_TO_DMA
17 select ARCH_HAS_SETUP_DMA_OPS
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
20 select ARCH_HAS_STRICT_MODULE_RWX if MMU
21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU
22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU
23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
25 select ARCH_HAVE_CUSTOM_GPIO_H
26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
35 select ARCH_USE_BUILTIN_BSWAP
36 select ARCH_USE_CMPXCHG_LOCKREF
37 select ARCH_USE_MEMTEST
38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
39 select ARCH_WANT_IPC_PARSE_VERSION
40 select ARCH_WANT_LD_ORPHAN_WARN
41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
42 select BUILDTIME_TABLE_SORT if MMU
43 select CLONE_BACKWARDS
44 select CPU_PM if SUSPEND || CPU_IDLE
45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
46 select DMA_DECLARE_COHERENT
47 select DMA_GLOBAL_POOL if !MMU
48 select DMA_OPS
49 select DMA_REMAP if MMU
50 select EDAC_SUPPORT
51 select EDAC_ATOMIC_SCRUB
52 select GENERIC_ALLOCATOR
53 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
54 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
55 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
56 select GENERIC_IRQ_IPI if SMP
57 select GENERIC_CPU_AUTOPROBE
58 select GENERIC_EARLY_IOREMAP
59 select GENERIC_IDLE_POLL_SETUP
60 select GENERIC_IRQ_PROBE
61 select GENERIC_IRQ_SHOW
62 select GENERIC_IRQ_SHOW_LEVEL
63 select GENERIC_LIB_DEVMEM_IS_ALLOWED
64 select GENERIC_PCI_IOMAP
65 select GENERIC_SCHED_CLOCK
66 select GENERIC_SMP_IDLE_THREAD
67 select HANDLE_DOMAIN_IRQ
68 select HARDIRQS_SW_RESEND
69 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
70 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
71 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
72 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
73 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
74 select HAVE_ARCH_MMAP_RND_BITS if MMU
75 select HAVE_ARCH_PFN_VALID
76 select HAVE_ARCH_SECCOMP
77 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
78 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
79 select HAVE_ARCH_TRACEHOOK
80 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
81 select HAVE_ARM_SMCCC if CPU_V7
82 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
83 select HAVE_CONTEXT_TRACKING
84 select HAVE_C_RECORDMCOUNT
85 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
86 select HAVE_DMA_CONTIGUOUS if MMU
87 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
88 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
89 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
90 select HAVE_EXIT_THREAD
91 select HAVE_FAST_GUP if ARM_LPAE
92 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
93 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
94 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
95 select HAVE_FUTEX_CMPXCHG if FUTEX
96 select HAVE_GCC_PLUGINS
97 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
98 select HAVE_IRQ_TIME_ACCOUNTING
99 select HAVE_KERNEL_GZIP
100 select HAVE_KERNEL_LZ4
101 select HAVE_KERNEL_LZMA
102 select HAVE_KERNEL_LZO
103 select HAVE_KERNEL_XZ
104 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
105 select HAVE_KRETPROBES if HAVE_KPROBES
106 select HAVE_MOD_ARCH_SPECIFIC
107 select HAVE_NMI
108 select HAVE_OPTPROBES if !THUMB2_KERNEL
109 select HAVE_PERF_EVENTS
110 select HAVE_PERF_REGS
111 select HAVE_PERF_USER_STACK_DUMP
112 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
113 select HAVE_REGS_AND_STACK_ACCESS_API
114 select HAVE_RSEQ
115 select HAVE_STACKPROTECTOR
116 select HAVE_SYSCALL_TRACEPOINTS
117 select HAVE_UID16
118 select HAVE_VIRT_CPU_ACCOUNTING_GEN
119 select IRQ_FORCED_THREADING
120 select MODULES_USE_ELF_REL
121 select NEED_DMA_MAP_STATE
122 select OF_EARLY_FLATTREE if OF
123 select OLD_SIGACTION
124 select OLD_SIGSUSPEND3
125 select PCI_SYSCALL if PCI
126 select PERF_USE_VMALLOC
127 select RTC_LIB
128 select SYS_SUPPORTS_APM_EMULATION
129 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
133 The ARM series is a line of low-power-consumption RISC chip designs
135 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
136 manufactured, but legacy ARM-based PC hardware remains popular in
145 select ARM_HAS_SG_CHAIN
146 select NEED_SG_DMA_LENGTH
174 select GENERIC_ALLOCATOR
239 Patch phys-to-virt and virt-to-phys translation functions at
243 This can only be used with non-XIP MMU kernels where the base
253 Select this when mach/io.h is required to provide special
260 Select this when mach/memory.h is required to provide special
288 bool "MMU-based Paged Memory Management Support"
291 Select if you want MMU-based virtualised addressing space
314 select ARCH_FLATMEM_ENABLE
315 select ARCH_SPARSEMEM_ENABLE
316 select ARCH_SELECT_MEMORY_MODEL
317 select ARM_HAS_SG_CHAIN
318 select ARM_PATCH_PHYS_VIRT
319 select AUTO_ZRELADDR
320 select TIMER_OF
321 select COMMON_CLK
322 select GENERIC_IRQ_MULTI_HANDLER
323 select HAVE_PCI
324 select PCI_DOMAINS_GENERIC if PCI
325 select SPARSE_IRQ
326 select USE_OF
329 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
331 select ARM_NVIC
332 select AUTO_ZRELADDR
333 select TIMER_OF
334 select COMMON_CLK
335 select CPU_V7M
336 select NO_IOPORT_MAP
337 select SPARSE_IRQ
338 select USE_OF
341 bool "EP93xx-based"
342 select ARCH_SPARSEMEM_ENABLE
343 select ARM_AMBA
345 select ARM_VIC
346 select GENERIC_IRQ_MULTI_HANDLER
347 select AUTO_ZRELADDR
348 select CLKSRC_MMIO
349 select CPU_ARM920T
350 select GPIOLIB
351 select HAVE_LEGACY_CLK
357 select CPU_SA110
358 select FOOTBRIDGE
359 select NEED_MACH_IO_H if !MMU
360 select NEED_MACH_MEMORY_H
366 bool "IOP32x-based"
368 select CPU_XSCALE
369 select GPIO_IOP
370 select GPIOLIB
371 select NEED_RET_TO_USER
372 select FORCE_PCI
373 select PLAT_IOP
379 bool "IXP4xx-based"
381 select ARCH_HAS_DMA_SET_COHERENT_MASK
382 select ARCH_SUPPORTS_BIG_ENDIAN
383 select CPU_XSCALE
384 select DMABOUNCE if PCI
385 select GENERIC_IRQ_MULTI_HANDLER
386 select GPIO_IXP4XX
387 select GPIOLIB
388 select HAVE_PCI
389 select IXP4XX_IRQ
390 select IXP4XX_TIMER
392 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY
393 select USB_EHCI_BIG_ENDIAN_DESC
394 select USB_EHCI_BIG_ENDIAN_MMIO
400 select CPU_PJ4
401 select GENERIC_IRQ_MULTI_HANDLER
402 select GPIOLIB
403 select HAVE_PCI
404 select MVEBU_MBUS
405 select PINCTRL
406 select PINCTRL_DOVE
407 select PLAT_ORION_LEGACY
408 select SPARSE_IRQ
409 select PM_GENERIC_DOMAINS if PM
414 bool "PXA2xx/PXA3xx-based"
416 select ARCH_MTD_XIP
417 select ARM_CPU_SUSPEND if PM
418 select AUTO_ZRELADDR
419 select COMMON_CLK
420 select CLKSRC_PXA
421 select CLKSRC_MMIO
422 select TIMER_OF
423 select CPU_XSCALE if !CPU_XSC3
424 select GENERIC_IRQ_MULTI_HANDLER
425 select GPIO_PXA
426 select GPIOLIB
427 select IRQ_DOMAIN
428 select PLAT_PXA
429 select SPARSE_IRQ
436 select ARCH_ACORN
437 select ARCH_MAY_HAVE_PC_FDC
438 select ARCH_SPARSEMEM_ENABLE
439 select ARM_HAS_SG_CHAIN
440 select CPU_SA110
441 select FIQ
442 select HAVE_PATA_PLATFORM
443 select ISA_DMA_API
444 select LEGACY_TIMER_TICK
445 select NEED_MACH_IO_H
446 select NEED_MACH_MEMORY_H
447 select NO_IOPORT_MAP
449 On the Acorn Risc-PC, Linux can support the internal IDE disk and
450 CD-ROM interface, serial and parallel port, and the floppy drive.
453 bool "SA1100-based"
454 select ARCH_MTD_XIP
455 select ARCH_SPARSEMEM_ENABLE
456 select CLKSRC_MMIO
457 select CLKSRC_PXA
458 select TIMER_OF if OF
459 select COMMON_CLK
460 select CPU_FREQ
461 select CPU_SA1100
462 select GENERIC_IRQ_MULTI_HANDLER
463 select GPIOLIB
464 select IRQ_DOMAIN
465 select ISA
466 select NEED_MACH_MEMORY_H
467 select SPARSE_IRQ
473 select ATAGS
474 select CLKSRC_SAMSUNG_PWM
475 select GPIO_SAMSUNG
476 select GPIOLIB
477 select GENERIC_IRQ_MULTI_HANDLER
478 select HAVE_S3C2410_I2C if I2C
479 select HAVE_S3C_RTC if RTC_CLASS
480 select NEED_MACH_IO_H
481 select S3C2410_WATCHDOG
482 select SAMSUNG_ATAGS
483 select USE_OF
484 select WATCHDOG
494 select ARCH_OMAP
495 select CLKSRC_MMIO
496 select GENERIC_IRQ_CHIP
497 select GENERIC_IRQ_MULTI_HANDLER
498 select GPIOLIB
499 select HAVE_LEGACY_CLK
500 select IRQ_DOMAIN
501 select NEED_MACH_IO_H if PCCARD
502 select NEED_MACH_MEMORY_H
503 select SPARSE_IRQ
517 select ARCH_MULTI_V4_V5
518 select CPU_FA526
523 select ARCH_MULTI_V4_V5
524 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
531 select ARCH_MULTI_V4_V5
532 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
541 select ARCH_MULTI_V6_V7
542 select CPU_V6K
545 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
547 select ARCH_MULTI_V6_V7
548 select CPU_V7
549 select HAVE_SMP
553 select MIGHT_HAVE_CACHE_L2X0
557 select ARCH_MULTI_V5
564 select ARM_AMBA
565 select ARM_GIC
566 select ARM_GIC_V2M if PCI
567 select ARM_GIC_V3
568 select ARM_GIC_V3_ITS if PCI
569 select ARM_PSCI
570 select HAVE_ARM_ARCH_TIMER
571 select ARCH_SUPPORTS_BIG_ENDIAN
574 # This is sorted alphabetically by mach-* pathname. However, plat-*
576 # plat- suffix) or along side the corresponding mach-* source.
578 source "arch/arm/mach-actions/Kconfig"
580 source "arch/arm/mach-alpine/Kconfig"
582 source "arch/arm/mach-artpec/Kconfig"
584 source "arch/arm/mach-asm9260/Kconfig"
586 source "arch/arm/mach-aspeed/Kconfig"
588 source "arch/arm/mach-at91/Kconfig"
590 source "arch/arm/mach-axxia/Kconfig"
592 source "arch/arm/mach-bcm/Kconfig"
594 source "arch/arm/mach-berlin/Kconfig"
596 source "arch/arm/mach-clps711x/Kconfig"
598 source "arch/arm/mach-cns3xxx/Kconfig"
600 source "arch/arm/mach-davinci/Kconfig"
602 source "arch/arm/mach-digicolor/Kconfig"
604 source "arch/arm/mach-dove/Kconfig"
606 source "arch/arm/mach-ep93xx/Kconfig"
608 source "arch/arm/mach-exynos/Kconfig"
610 source "arch/arm/mach-footbridge/Kconfig"
612 source "arch/arm/mach-gemini/Kconfig"
614 source "arch/arm/mach-highbank/Kconfig"
616 source "arch/arm/mach-hisi/Kconfig"
618 source "arch/arm/mach-imx/Kconfig"
620 source "arch/arm/mach-integrator/Kconfig"
622 source "arch/arm/mach-iop32x/Kconfig"
624 source "arch/arm/mach-ixp4xx/Kconfig"
626 source "arch/arm/mach-keystone/Kconfig"
628 source "arch/arm/mach-lpc32xx/Kconfig"
630 source "arch/arm/mach-mediatek/Kconfig"
632 source "arch/arm/mach-meson/Kconfig"
634 source "arch/arm/mach-milbeaut/Kconfig"
636 source "arch/arm/mach-mmp/Kconfig"
638 source "arch/arm/mach-moxart/Kconfig"
640 source "arch/arm/mach-mstar/Kconfig"
642 source "arch/arm/mach-mv78xx0/Kconfig"
644 source "arch/arm/mach-mvebu/Kconfig"
646 source "arch/arm/mach-mxs/Kconfig"
648 source "arch/arm/mach-nomadik/Kconfig"
650 source "arch/arm/mach-npcm/Kconfig"
652 source "arch/arm/mach-nspire/Kconfig"
654 source "arch/arm/plat-omap/Kconfig"
656 source "arch/arm/mach-omap1/Kconfig"
658 source "arch/arm/mach-omap2/Kconfig"
660 source "arch/arm/mach-orion5x/Kconfig"
662 source "arch/arm/mach-oxnas/Kconfig"
664 source "arch/arm/mach-pxa/Kconfig"
665 source "arch/arm/plat-pxa/Kconfig"
667 source "arch/arm/mach-qcom/Kconfig"
669 source "arch/arm/mach-rda/Kconfig"
671 source "arch/arm/mach-realtek/Kconfig"
673 source "arch/arm/mach-realview/Kconfig"
675 source "arch/arm/mach-rockchip/Kconfig"
677 source "arch/arm/mach-s3c/Kconfig"
679 source "arch/arm/mach-s5pv210/Kconfig"
681 source "arch/arm/mach-sa1100/Kconfig"
683 source "arch/arm/mach-shmobile/Kconfig"
685 source "arch/arm/mach-socfpga/Kconfig"
687 source "arch/arm/mach-spear/Kconfig"
689 source "arch/arm/mach-sti/Kconfig"
691 source "arch/arm/mach-stm32/Kconfig"
693 source "arch/arm/mach-sunxi/Kconfig"
695 source "arch/arm/mach-tegra/Kconfig"
697 source "arch/arm/mach-uniphier/Kconfig"
699 source "arch/arm/mach-ux500/Kconfig"
701 source "arch/arm/mach-versatile/Kconfig"
703 source "arch/arm/mach-vexpress/Kconfig"
705 source "arch/arm/mach-vt8500/Kconfig"
707 source "arch/arm/mach-zynq/Kconfig"
709 # ARMv7-M architecture
713 select ARCH_HAS_RESET_CONTROLLER
714 select ARM_AMBA
715 select CLKSRC_LPC32XX
716 select PINCTRL
718 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
724 select ARM_AMBA
725 select CLKSRC_MPS2
727 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
728 with a range of available cores like Cortex-M3/M4/M7.
742 select CLKSRC_MMIO
743 select COMMON_CLK
744 select GENERIC_IRQ_CHIP
745 select IRQ_DOMAIN
749 select PLAT_ORION
768 source "arch/arm/Kconfig-nommu"
786 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
789 Executing a SWP instruction to read-only memory does not set bit 11
807 This option enables the workaround for the 430973 Cortex-A8
810 same virtual address, whether due to self-modifying code or virtual
811 to physical address re-mapping, Cortex-A8 does not recover from the
812 stale interworking branch prediction. This results in Cortex-A8
817 available in non-secure mode.
824 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
831 register may not be available in non-secure mode.
838 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
842 workaround disables the write-allocate mode for the L2 cache via the
844 may not be available in non-secure mode.
851 This option enables the workaround for the 742230 Cortex-A9
855 the diagnostic register of the Cortex-A9 which causes the DMB
864 This option enables the workaround for the 742231 Cortex-A9
866 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
871 register of the Cortex-A9 which reduces the linefill issuing
879 This option enables the workaround for the 643719 Cortex-A9 (prior to
889 This option enables the workaround for the 720789 Cortex-A9 (prior to
902 This option enables the workaround for the 743622 Cortex-A9
904 optimisation in the Cortex-A9 Store Buffer may lead to data
906 register of the Cortex-A9 which disables the Store Buffer
916 This option enables the workaround for the 751472 Cortex-A9 (prior
926 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
929 can populate the micro-TLB with a stale entry which may be hit with
937 This option enables the workaround for the 754327 Cortex-A9 (prior to
945 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
950 hit-under-miss enabled). It sets the undocumented bit 31 in
952 register, thus disabling hit-under-miss without putting the
961 affecting Cortex-A9 MPCore with two or more processors (all
974 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
981 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
984 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
994 This option enables the workaround for the 773022 Cortex-A15
1004 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1006 - Cortex-A12 852422: Execution of a sequence of instructions might
1008 any Cortex-A12 cores yet.
1017 This option enables the workaround for the 821420 Cortex-A12
1021 deadlock when the VMOV instructions are issued out-of-order.
1027 This option enables the workaround for the 825619 Cortex-A12
1030 and Device/Strongly-Ordered loads and stores might cause deadlock
1036 This option enables the workaround for the 857271 Cortex-A12
1044 This option enables the workaround for the 852421 Cortex-A17
1054 - Cortex-A17 852423: Execution of a sequence of instructions might
1056 any Cortex-A17 cores yet.
1057 This is identical to Cortex-A12 erratum 852422. It is a separate
1058 config option from the A12 erratum due to the way errata are checked
1065 This option enables the workaround for the 857272 Cortex-A17 erratum.
1067 This is identical to Cortex-A12 erratum 857271. It is a separate
1068 config option from the A12 erratum due to the way errata are checked
1081 name of a bus system, i.e. the way the CPU talks to the other stuff
1086 # Select ISA DMA controller support
1089 select ISA_DMA_API
1091 # Select ISA DMA interface
1102 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1108 However, because of this erratum, an L2 set/way cache maintenance
1109 operation can overtake an L1 set/way cache maintenance operation.
1110 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1120 This option should be selected by machines which have an SMP-
1123 The only effect of this option is to make the SMP-related
1127 bool "Symmetric Multi-Processing"
1131 select IRQ_WORK
1137 If you say N here, the kernel will run on uni- and multiprocessor
1143 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1144 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1145 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1154 SMP kernels contain instructions which fail on non-SMP processors.
1171 bool "Multi-core scheduler support"
1174 Multi-core scheduler support improves the CPU scheduler's decision
1175 making when dealing with multi-core CPU chips at a cost of slightly
1194 select ARM_ARCH_TIMER
1204 bool "Multi-Cluster Power Management"
1208 for (multi-)cluster based systems, such as big.LITTLE based
1217 Platforms with 3 or 4 clusters that use MCPM must select this
1223 select MCPM
1231 select CPU_PM
1250 Select the desired split between kernel and user memory.
1284 int "Maximum number of CPUs (2-32)"
1292 debugging is enabled, which uses half of the per-CPU fixmap
1296 bool "Support for hot-pluggable CPUs"
1298 select GENERIC_IRQ_MIGRATION
1306 select ARM_PSCI_FW
1309 implementing the PSCI specification for CPU-centric power
1378 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1381 select ARM_UNWIND
1384 Thumb-2 mode.
1435 selected, since there is no way yet to sensibly distinguish
1452 select SPARSEMEM_STATIC if SPARSEMEM
1457 select KMAP_LOCAL
1473 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1481 user-space 2nd level page tables to reside in high memory.
1484 bool "Enable use of CPU domains to implement privileged no-access"
1490 use-after-free bugs becoming an exploitable privilege escalation
1494 CPUs with low-vector mappings use a best-efforts implementation.
1519 Disabling this is usually safe for small single-platform
1540 select HAVE_PROC_CPU if PROC_FS
1544 address divisible by 4. On 32-bit ARM processors, these non-aligned
1547 correct operation of some network protocols. With an IP-only
1556 cores where a 8-word STM instruction give significantly higher
1563 However, if the CPU data cache is using a write-allocate mode,
1575 select PARAVIRT
1577 Select this option to enable fine granularity task steal time
1594 select ARCH_DMA_ADDR_T_64BIT
1595 select ARM_PSCI
1596 select SWIOTLB
1597 select SWIOTLB_XEN
1598 select PARAVIRT
1605 select GCC_PLUGIN_ARM_SSP_PER_TASK
1623 select IRQ_DOMAIN
1624 select OF
1632 This is the traditional way of passing data to the kernel at boot
1639 bool "Provide old way to pass kernel parameters"
1643 Some old boot loaders still use this way.
1651 The physical address at which the ROM-able zImage is to be
1653 ROM-able zImage formats normally set this to a suitable
1663 for the ROM-able zImage which must be available while the
1666 Platforms which normally make use of ROM-able zImage formats
1718 Uses the command-line options passed by the boot loader instead of
1725 The command-line arguments provided by the boot loader will be
1734 On some architectures (e.g. CATS), there is currently no way
1736 architectures, you should supply some command-line options at build
1748 Uses the command-line options passed by the boot loader. If
1755 The command-line arguments provided by the boot loader will be
1764 command-line options your boot loader passes to the kernel.
1768 bool "Kernel Execute-In-Place from ROM"
1771 Execute-In-Place allows the kernel to run from non-volatile storage
1774 to RAM. Read-write sections, such as the data section and stack,
1800 select ZLIB_INFLATE
1812 select KEXEC_CORE
1836 loaded in the main kernel with kexec-tools into a specially
1841 For more details see Documentation/admin-guide/kdump/kdump.rst
1848 will be determined at run-time, either by masking the current IP
1859 select UCS2_STRING
1860 select EFI_PARAMS_FROM_FDT
1861 select EFI_STUB
1862 select EFI_GENERIC_STUB
1863 select EFI_RUNTIME_WRAPPERS
1866 by UEFI firmware (such as non-volatile variables, realtime
1881 continue to boot on existing non-UEFI platforms.
1887 to be enabled much earlier than we do on ARM, which is non-trivial.
1910 your machine has an FPA or floating point co-processor podule.
1919 Say Y to include 80-bit support in the kernel floating-point
1920 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1921 Note that gcc does not generate 80-bit operations by default,
1934 It is very simple, and approximately 3-6 times faster than NWFPE.
1942 bool "VFP-format floating point maths"
1948 Please see <file:Documentation/arm/vfp/release-notes.rst> for