Lines Matching +full:cpu +full:- +full:centric
1 # SPDX-License-Identifier: GPL-2.0
133 The ARM series is a line of low-power-consumption RISC chip designs
135 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
136 manufactured, but legacy ARM-based PC hardware remains popular in
239 Patch phys-to-virt and virt-to-phys translation functions at
243 This can only be used with non-XIP MMU kernels where the base
288 bool "MMU-based Paged Memory Management Support"
291 Select if you want MMU-based virtualised addressing space
329 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
341 bool "EP93xx-based"
366 bool "IOP32x-based"
379 bool "IXP4xx-based"
414 bool "PXA2xx/PXA3xx-based"
449 On the Acorn Risc-PC, Linux can support the internal IDE disk and
450 CD-ROM interface, serial and parallel port, and the floppy drive.
453 bool "SA1100-based"
512 comment "CPU Core family selection"
545 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
574 # This is sorted alphabetically by mach-* pathname. However, plat-*
576 # plat- suffix) or along side the corresponding mach-* source.
578 source "arch/arm/mach-actions/Kconfig"
580 source "arch/arm/mach-alpine/Kconfig"
582 source "arch/arm/mach-artpec/Kconfig"
584 source "arch/arm/mach-asm9260/Kconfig"
586 source "arch/arm/mach-aspeed/Kconfig"
588 source "arch/arm/mach-at91/Kconfig"
590 source "arch/arm/mach-axxia/Kconfig"
592 source "arch/arm/mach-bcm/Kconfig"
594 source "arch/arm/mach-berlin/Kconfig"
596 source "arch/arm/mach-clps711x/Kconfig"
598 source "arch/arm/mach-cns3xxx/Kconfig"
600 source "arch/arm/mach-davinci/Kconfig"
602 source "arch/arm/mach-digicolor/Kconfig"
604 source "arch/arm/mach-dove/Kconfig"
606 source "arch/arm/mach-ep93xx/Kconfig"
608 source "arch/arm/mach-exynos/Kconfig"
610 source "arch/arm/mach-footbridge/Kconfig"
612 source "arch/arm/mach-gemini/Kconfig"
614 source "arch/arm/mach-highbank/Kconfig"
616 source "arch/arm/mach-hisi/Kconfig"
618 source "arch/arm/mach-imx/Kconfig"
620 source "arch/arm/mach-integrator/Kconfig"
622 source "arch/arm/mach-iop32x/Kconfig"
624 source "arch/arm/mach-ixp4xx/Kconfig"
626 source "arch/arm/mach-keystone/Kconfig"
628 source "arch/arm/mach-lpc32xx/Kconfig"
630 source "arch/arm/mach-mediatek/Kconfig"
632 source "arch/arm/mach-meson/Kconfig"
634 source "arch/arm/mach-milbeaut/Kconfig"
636 source "arch/arm/mach-mmp/Kconfig"
638 source "arch/arm/mach-moxart/Kconfig"
640 source "arch/arm/mach-mstar/Kconfig"
642 source "arch/arm/mach-mv78xx0/Kconfig"
644 source "arch/arm/mach-mvebu/Kconfig"
646 source "arch/arm/mach-mxs/Kconfig"
648 source "arch/arm/mach-nomadik/Kconfig"
650 source "arch/arm/mach-npcm/Kconfig"
652 source "arch/arm/mach-nspire/Kconfig"
654 source "arch/arm/plat-omap/Kconfig"
656 source "arch/arm/mach-omap1/Kconfig"
658 source "arch/arm/mach-omap2/Kconfig"
660 source "arch/arm/mach-orion5x/Kconfig"
662 source "arch/arm/mach-oxnas/Kconfig"
664 source "arch/arm/mach-pxa/Kconfig"
665 source "arch/arm/plat-pxa/Kconfig"
667 source "arch/arm/mach-qcom/Kconfig"
669 source "arch/arm/mach-rda/Kconfig"
671 source "arch/arm/mach-realtek/Kconfig"
673 source "arch/arm/mach-realview/Kconfig"
675 source "arch/arm/mach-rockchip/Kconfig"
677 source "arch/arm/mach-s3c/Kconfig"
679 source "arch/arm/mach-s5pv210/Kconfig"
681 source "arch/arm/mach-sa1100/Kconfig"
683 source "arch/arm/mach-shmobile/Kconfig"
685 source "arch/arm/mach-socfpga/Kconfig"
687 source "arch/arm/mach-spear/Kconfig"
689 source "arch/arm/mach-sti/Kconfig"
691 source "arch/arm/mach-stm32/Kconfig"
693 source "arch/arm/mach-sunxi/Kconfig"
695 source "arch/arm/mach-tegra/Kconfig"
697 source "arch/arm/mach-uniphier/Kconfig"
699 source "arch/arm/mach-ux500/Kconfig"
701 source "arch/arm/mach-versatile/Kconfig"
703 source "arch/arm/mach-vexpress/Kconfig"
705 source "arch/arm/mach-vt8500/Kconfig"
707 source "arch/arm/mach-zynq/Kconfig"
709 # ARMv7-M architecture
718 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
727 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
728 with a range of available cores like Cortex-M3/M4/M7.
765 running on a CPU that supports it.
768 source "arch/arm/Kconfig-nommu"
772 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
779 instructions. This sensitivity can result in a CPU hang scenario.
786 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
789 Executing a SWP instruction to read-only memory does not set bit 11
807 This option enables the workaround for the 430973 Cortex-A8
810 same virtual address, whether due to self-modifying code or virtual
811 to physical address re-mapping, Cortex-A8 does not recover from the
812 stale interworking branch prediction. This results in Cortex-A8
817 available in non-secure mode.
824 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
831 register may not be available in non-secure mode.
838 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
842 workaround disables the write-allocate mode for the L2 cache via the
844 may not be available in non-secure mode.
851 This option enables the workaround for the 742230 Cortex-A9
855 the diagnostic register of the Cortex-A9 which causes the DMB
864 This option enables the workaround for the 742231 Cortex-A9
866 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
869 replaced from one of the CPUs at the same time as another CPU is
871 register of the Cortex-A9 which reduces the linefill issuing
879 This option enables the workaround for the 643719 Cortex-A9 (prior to
889 This option enables the workaround for the 720789 Cortex-A9 (prior to
902 This option enables the workaround for the 743622 Cortex-A9
904 optimisation in the Cortex-A9 Store Buffer may lead to data
906 register of the Cortex-A9 which disables the Store Buffer
916 This option enables the workaround for the 751472 Cortex-A9 (prior
919 operation is received by a CPU before the ICIALLUIS has completed,
926 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
929 can populate the micro-TLB with a stale entry which may be hit with
937 This option enables the workaround for the 754327 Cortex-A9 (prior to
945 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
950 hit-under-miss enabled). It sets the undocumented bit 31 in
952 register, thus disabling hit-under-miss without putting the
961 affecting Cortex-A9 MPCore with two or more processors (all
974 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
981 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
984 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
994 This option enables the workaround for the 773022 Cortex-A15
1004 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1006 - Cortex-A12 852422: Execution of a sequence of instructions might
1007 lead to either a data corruption or a CPU deadlock. Not fixed in
1008 any Cortex-A12 cores yet.
1017 This option enables the workaround for the 821420 Cortex-A12
1021 deadlock when the VMOV instructions are issued out-of-order.
1027 This option enables the workaround for the 825619 Cortex-A12
1030 and Device/Strongly-Ordered loads and stores might cause deadlock
1033 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1036 This option enables the workaround for the 857271 Cortex-A12
1037 (all revs) erratum. Under very rare timing conditions, the CPU might
1044 This option enables the workaround for the 852421 Cortex-A17
1054 - Cortex-A17 852423: Execution of a sequence of instructions might
1055 lead to either a data corruption or a CPU deadlock. Not fixed in
1056 any Cortex-A17 cores yet.
1057 This is identical to Cortex-A12 erratum 852422. It is a separate
1062 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1065 This option enables the workaround for the 857272 Cortex-A17 erratum.
1067 This is identical to Cortex-A12 erratum 857271. It is a separate
1081 name of a bus system, i.e. the way the CPU talks to the other stuff
1110 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1120 This option should be selected by machines which have an SMP-
1121 capable CPU.
1123 The only effect of this option is to make the SMP-related
1127 bool "Symmetric Multi-Processing"
1133 This enables support for systems with more than one CPU. If you have
1134 a system with only one CPU, say N. If you have a system with more
1135 than one CPU, say Y.
1137 If you say N here, the kernel will run on uni- and multiprocessor
1138 machines, but will use only one CPU of a multiprocessor machine. If
1143 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1144 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1145 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1154 SMP kernels contain instructions which fail on non-SMP processors.
1162 bool "Support cpu topology definition"
1166 Support ARM cpu topology definition. The MPIDR register defines
1167 affinity between processors which is then used to describe the cpu
1171 bool "Multi-core scheduler support"
1174 Multi-core scheduler support improves the CPU scheduler's decision
1175 making when dealing with multi-core CPU chips at a cost of slightly
1182 Improves the CPU scheduler's decision making when dealing with
1204 bool "Multi-Cluster Power Management"
1208 for (multi-)cluster based systems, such as big.LITTLE based
1284 int "Maximum number of CPUs (2-32)"
1292 debugging is enabled, which uses half of the per-CPU fixmap
1296 bool "Support for hot-pluggable CPUs"
1301 can be controlled through /sys/devices/system/cpu.
1309 implementing the PSCI specification for CPU-centric power
1378 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1384 Thumb-2 mode.
1401 with the sdiv or udiv plus "bx lr" instructions when the CPU
1473 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1481 user-space 2nd level page tables to reside in high memory.
1484 bool "Enable use of CPU domains to implement privileged no-access"
1490 use-after-free bugs becoming an exploitable privilege escalation
1494 CPUs with low-vector mappings use a best-efforts implementation.
1519 Disabling this is usually safe for small single-platform
1544 address divisible by 4. On 32-bit ARM processors, these non-aligned
1547 correct operation of some network protocols. With an IP-only
1555 Implement faster copy_to_user and clear_user methods for CPU
1556 cores where a 8-word STM instruction give significantly higher
1563 However, if the CPU data cache is using a write-allocate mode,
1651 The physical address at which the ROM-able zImage is to be
1653 ROM-able zImage formats normally set this to a suitable
1663 for the ROM-able zImage which must be available while the
1666 Platforms which normally make use of ROM-able zImage formats
1718 Uses the command-line options passed by the boot loader instead of
1725 The command-line arguments provided by the boot loader will be
1736 architectures, you should supply some command-line options at build
1748 Uses the command-line options passed by the boot loader. If
1755 The command-line arguments provided by the boot loader will be
1764 command-line options your boot loader passes to the kernel.
1768 bool "Kernel Execute-In-Place from ROM"
1771 Execute-In-Place allows the kernel to run from non-volatile storage
1772 directly addressable by the CPU, such as NOR flash. This saves RAM
1774 to RAM. Read-write sections, such as the data section and stack,
1836 loaded in the main kernel with kexec-tools into a specially
1841 For more details see Documentation/admin-guide/kdump/kdump.rst
1848 will be determined at run-time, either by masking the current IP
1866 by UEFI firmware (such as non-volatile variables, realtime
1881 continue to boot on existing non-UEFI platforms.
1887 to be enabled much earlier than we do on ARM, which is non-trivial.
1891 menu "CPU Power Management"
1910 your machine has an FPA or floating point co-processor podule.
1919 Say Y to include 80-bit support in the kernel floating-point
1920 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1921 Note that gcc does not generate 80-bit operations by default,
1934 It is very simple, and approximately 3-6 times faster than NWFPE.
1942 bool "VFP-format floating point maths"
1948 Please see <file:Documentation/arm/vfp/release-notes.rst> for