16 #include <asm/mmu.h>
85 	 * If Not already present get a free slot from MMU.  in tlb_entry_insert()
97 	 * Commit the Entry to MMU  in tlb_entry_insert()
129  * Un-conditionally (without lookup) erase the entire MMU contents
134 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;  in local_flush_tlb_all()  local
137 	int num_tlb = mmu->sets * mmu->ways;  in local_flush_tlb_all()
180 	 * Only for fork( ) do we need to move parent to a new MMU ctxt,  in local_flush_tlb_mm()
243 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
272  * Delete TLB entry in MMU for a given page (??? address)
401 	 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)  in create_tlb()
405 	 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.  in create_tlb()
441 	 * ARC MMU provides fully orthogonal access bits for K/U mode,  in create_tlb()
443 	 * Here we convert 3 PTE bits into 6 MMU bits:  in create_tlb()
463  *  -pre-install the corresponding TLB entry into MMU
519  *  - MMU page size (typical 8K, RTL fixed)
565 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;  in read_decode_mmu_bcr()  local
589 	mmu->ver = (tmp >> 24);  in read_decode_mmu_bcr()
591 	if (is_isa_arcompact() && mmu->ver == 3) {  in read_decode_mmu_bcr()
593 		mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);  in read_decode_mmu_bcr()
594 		mmu->sets = 1 << mmu3->sets;  in read_decode_mmu_bcr()
595 		mmu->ways = 1 << mmu3->ways;  in read_decode_mmu_bcr()
596 		mmu->u_dtlb = mmu3->u_dtlb;  in read_decode_mmu_bcr()
597 		mmu->u_itlb = mmu3->u_itlb;  in read_decode_mmu_bcr()
598 		mmu->sasid = mmu3->sasid;  in read_decode_mmu_bcr()
601 		mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);  in read_decode_mmu_bcr()
602 		mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);  in read_decode_mmu_bcr()
603 		mmu->sets = 64 << mmu4->n_entry;  in read_decode_mmu_bcr()
604 		mmu->ways = mmu4->n_ways * 2;  in read_decode_mmu_bcr()
605 		mmu->u_dtlb = mmu4->u_dtlb * 4;  in read_decode_mmu_bcr()
606 		mmu->u_itlb = mmu4->u_itlb * 4;  in read_decode_mmu_bcr()
607 		mmu->sasid = mmu4->sasid;  in read_decode_mmu_bcr()
608 		pae_exists = mmu->pae = mmu4->pae;  in read_decode_mmu_bcr()
615 	struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;  in arc_mmu_mumbojumbo()
624 		      "MMU [v%x]\t: %dk PAGE, %s, swalk %d lvl, JTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n",  in arc_mmu_mumbojumbo()
640 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;  in arc_mmu_init()  local
658 	 * Ensure that MMU features assumed by kernel exist in hardware.  in arc_mmu_init()
663 	if (is_isa_arcompact() && mmu->ver == 3)  in arc_mmu_init()
665 	else if (is_isa_arcv2() && mmu->ver >= 4)  in arc_mmu_init()
669 		panic("MMU ver %d doesn't match kernel built for\n", mmu->ver);  in arc_mmu_init()
671 	if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))  in arc_mmu_init()
672 		panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));  in arc_mmu_init()
675 	    mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE))  in arc_mmu_init()
676 		panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",  in arc_mmu_init()
679 	if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)  in arc_mmu_init()
682 	/* Enable the MMU with ASID 0 */  in arc_mmu_init()
685 	/* cache the pgd pointer in MMU SCRATCH reg (ARCv2 only) */  in arc_mmu_init()
704  * MMU cmd getIndex(vaddr) abstracts that out.
707 #define SET_WAY_TO_IDX(mmu, set, way)  ((set) * mmu->ways + (way))  argument
709 /* Handling of Duplicate PD (TLB entry) in MMU.
711  * -MMU complaints not at the time of duplicate PD installation, but at the
722 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;  in do_tlb_overlap_fault()  local
724 	int set, n_ways = mmu->ways;  in do_tlb_overlap_fault()
727 	BUG_ON(mmu->ways > 4);  in do_tlb_overlap_fault()
732 	for (set = 0; set < mmu->sets; set++) {  in do_tlb_overlap_fault()
740 					  SET_WAY_TO_IDX(mmu, set, way));  in do_tlb_overlap_fault()
773 						SET_WAY_TO_IDX(mmu, set, way));  in do_tlb_overlap_fault()