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1 .. SPDX-License-Identifier: GPL-2.0
10 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
11           - Tony Luck <tony.luck@intel.com>
16 A split lock is any atomic operation whose operand crosses two cache lines.
17 Since the operand spans two cache lines and the operation must be atomic,
18 the system locks the bus while the CPU accesses the two cache lines.
21 memory or any locked access to non-WB memory. This is typically thousands of
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40 Some CPUs have the ability to notify the kernel by an #DB trap after a user
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61 |fatal		   |Kernel OOPs			|Send SIGBUS to user.	|
62 |		   |Send SIGBUS to user		|			|
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79 "untrusted" user processes on other cores. The hard real time cannot afford
82 solutions as they have no way to prevent the "untrusted" user code from
86 It's also useful for general computing to prevent guests or user
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