Lines Matching +full:2 +full:- +full:dimensional
1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
31 - dirty tracking:
33 and framebuffer-based displays
34 - footprint:
37 - reliability:
56 tdp two dimensional paging (vendor neutral term for NPT and EPT)
62 The mmu supports first-generation mmu hardware, which allows an atomic switch
64 two-dimensional paging (AMD's NPT and Intel's EPT). The emulated hardware
65 it exposes is the traditional 2/3/4 level x86 mmu, with support for global
76 - when guest paging is disabled, we translate guest physical addresses to
77 host physical addresses (gpa->hpa)
78 - when guest paging is enabled, we translate guest virtual addresses, to
79 guest physical addresses, to host physical addresses (gva->gpa->hpa)
80 - when the guest launches a guest of its own, we translate nested guest
82 addresses, to host physical addresses (ngva->ngpa->gpa->hpa)
85 that support only 1 (traditional) and 2 (tdp) translations. When the
94 addresses (gpa->hva); note that two gpas may alias to the same hva, but not
108 - writes to control registers (especially cr3)
109 - invlpg/invlpga instruction execution
110 - access to missing or protected translations
114 - changes in the gpa->hpa translation (either through gpa->hva changes or
115 through hva->hpa changes)
116 - memory pressure (the shrinker)
133 The following table shows translations encoded by leaf ptes, with higher-level
136 Non-nested guests::
138 nonpaging: gpa->hpa
139 paging: gva->gpa->hpa
140 paging, tdp: (gva->)gpa->hpa
144 non-tdp: ngva->gpa->hpa (*)
145 tdp: (ngva->)ngpa->gpa->hpa
147 (*) the guest hypervisor will encode the ngva->gpa translation into its page
153 1=4k sptes, 2=2M sptes, 3=1G sptes, etc.
157 host pages, and gpa->hpa translations when NPT or EPT is active.
159 by role.level (2MB for first level, 1GB for second level, 0.5TB for third
164 When role.gpte_is_8_bytes=0, the guest uses 32-bit gptes while the host uses 64-bit
167 For first-level shadow pages, role.quadrant can be 0 or 1 and denotes the
168 first or second 512-gpte block in the guest page table. For second-level
169 page tables, each 32-bit gpte is converted to two 64-bit sptes
170 (since each first-level guest page is shadowed by two first-level
182 if 64-bit gptes are in use, '0' if 32-bit gptes are in use.
209 A pageful of 64-bit sptes containing the translations for this page.
211 The page pointed to by spt will have its page->private pointing back
213 sptes in spt point either at guest pages, or at lower-level shadow pages.
214 Specifically, if sp1 and sp2 are shadow pages, then sp1->spt[n] may point
215 at __pa(sp2->spt). sp2 will point back at sp1 through parent_pte.
247 Only present on 32-bit hosts, where a 64-bit spte cannot be written
249 to detect in-progress updates and retry them until the writer has
253 emulations if the page needs to be write-protected (see "Synchronized
256 possible for non-leafs. This field counts the number of emulations
293 - guest page fault (or npt page fault, or ept violation)
297 - a true guest fault (the guest translation won't allow the access) (*)
298 - access to a missing translation
299 - access to a protected translation
300 - when logging dirty pages, memory is write protected
301 - synchronized shadow pages are write protected (*)
302 - access to untranslatable memory (mmio)
308 - if the RSV bit of the error code is set, the page fault is caused by guest
311 - walk shadow page table
312 - check for valid generation number in the spte (see "Fast invalidation of
314 - cache the information to vcpu->arch.mmio_gva, vcpu->arch.mmio_access and
315 vcpu->arch.mmio_gfn, and call the emulator
317 - If both P bit and R/W bit of error code are set, this could possibly
321 - if needed, walk the guest page tables to determine the guest translation
322 (gva->gpa or ngpa->gpa)
324 - if permissions are insufficient, reflect the fault back to the guest
326 - determine the host page
328 - if this is an mmio request, there is no host page; cache the info to
329 vcpu->arch.mmio_gva, vcpu->arch.mmio_access and vcpu->arch.mmio_gfn
331 - walk the shadow page table to find the spte for the translation,
334 - If this is an mmio request, cache the mmio info to the spte and set some
337 - try to unsynchronize the page
339 - if successful, we can let the guest continue and modify the gpte
341 - emulate the instruction
343 - if failed, unshadow the page and let the guest continue
345 - update any translations that were modified by the instruction
349 - walk the shadow page hierarchy and drop affected translations
350 - try to reinstantiate the indicated translation in the hope that the
355 - mov to cr3
357 - look up new shadow roots
358 - synchronize newly reachable shadow pages
360 - mov to cr0/cr4/efer
362 - set up mmu context for new paging mode
363 - look up new shadow roots
364 - synchronize newly reachable shadow pages
368 - mmu notifier called with updated hva
369 - look up affected sptes through reverse map
370 - drop (or update) translations
384 - kernel write fault: spte.u=0, spte.w=1 (allows full kernel access,
386 - read fault: spte.u=1, spte.w=0 (allows full read access, disallows kernel
393 - if CR4.SMEP is enabled: since we've turned the page into a kernel page,
398 - if CR4.SMAP is disabled: since the page has been changed to a kernel
407 with one value of cr0.wp cannot be used when cr0.wp has a different value -
417 Supported page sizes include 4k, 2M, 4M, and 1G. 4M pages are treated as
418 two separate 2M pages, on both guest and host, since the mmu always uses PAE
423 - the spte must point to a large host page
424 - the guest pte must be a large pte of at least equivalent size (if tdp is
426 - if the spte will be writeable, the large page frame may not overlap any
427 write-protected pages
428 - the guest page must be wholly contained by a single memory slot
430 To check the last two conditions, the mmu maintains a ->disallow_lpage set of
434 artificially inflated ->disallow_lpages so they can never be instantiated.
447 kvm_memslots(kvm)->generation, and increased whenever guest memory info
455 Since only 18 bits are used to store generation-number on mmio spte, all
461 out-of-date information, but with an up-to-date generation number.
464 returns; thus, bit 63 of kvm_memslots(kvm)->generation set to 1 only during a
467 this without losing a bit in the MMIO spte. The "update in-progress" bit of the
470 spte while an update is in-progress, the next access to the spte will always be
472 miss due to the in-progress flag diverging, while an access after the update
479 - NPT presentation from KVM Forum 2008
480 https://www.linux-kvm.org/images/c/c8/KvmForum2008%24kdf2008_21.pdf