Lines Matching refs:Feature

2 FPGA Device Feature List (DFL) Framework Overview
12 The Device Feature List (DFL) FPGA framework (and drivers according to
20 Device Feature List (DFL) Overview
22 Device Feature List (DFL) defines a linked list of feature headers within the
32  +----------+  |   | Feature  |  |   | Feature  |  |   | Feature  |
38  +----------+  |   | Feature  |      | Feature  |      | Feature  |
66 Feature Header (Next_DFH) pointer.
68 Each FIU, AFU and Private Feature could implement its own functional registers.
70 e.g. FME Header Register Set, and the one for Private Feature, is named as
71 Feature Register Set, e.g. FME Partial Reconfiguration Feature Register Set.
73 This Device Feature List provides a way of linking features together, it's
189                  | FPGA Container Device |    Device Feature List
203 given Device Feature Lists and create platform devices for feature devices
260 Feature Lists, as illustrated below:
502 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)