Lines Matching +full:hardware +full:- +full:accelerated
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
13 this framework) hides the very details of low layer hardware and provides
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
29 +----------+ +-->+----------+ +-->+----------+ +-->+----------+
32 +----------+ | | Feature | | | Feature | | | Feature |
33 | Next_DFH |--+ +----------+ | +----------+ | +----------+
34 +----------+ | Next_DFH |--+ | Next_DFH |--+ | Next_DFH |--> NULL
35 | ID | +----------+ +----------+ +----------+
36 +----------+ | ID | | ID | | ID |
37 | Next_AFU |--+ +----------+ +----------+ +----------+
38 +----------+ | | Feature | | Feature | | Feature |
41 | Set | | +----------+ +----------+ +----------+
42 +----------+ | Header
43 +-->+----------+
46 +----------+
47 | Next_DFH |--> NULL
48 +----------+
50 +----------+
54 +----------+
60 Accelerated Function Unit (AFU) represents an FPGA programmable region and
78 FIU - FME (FPGA Management Engine)
83 User-space applications can acquire exclusive access to the FME using open(),
88 - Get driver API version (DFL_FPGA_GET_API_VERSION)
89 - Check for extensions (DFL_FPGA_CHECK_EXTENSION)
90 - Program bitstream (DFL_FPGA_FME_PORT_PR)
91 - Assign port to PF (DFL_FPGA_FME_PORT_ASSIGN)
92 - Release port from PF (DFL_FPGA_FME_PORT_RELEASE)
93 - Get number of irqs of FME global error (DFL_FPGA_FME_ERR_GET_IRQ_NUM)
94 - Set interrupt trigger for FME error (DFL_FPGA_FME_ERR_SET_IRQ)
97 (/sys/class/fpga_region/regionX/dfl-fme.n/):
112 hardware, and clear the logged errors.
130 FIU - PORT
141 used for accelerator-specific control registers.
143 User-space applications can acquire exclusive access to an AFU attached to a
148 - Get driver API version (DFL_FPGA_GET_API_VERSION)
149 - Check for extensions (DFL_FPGA_CHECK_EXTENSION)
150 - Get port info (DFL_FPGA_PORT_GET_INFO)
151 - Get MMIO region info (DFL_FPGA_PORT_GET_REGION_INFO)
152 - Map DMA buffer (DFL_FPGA_PORT_DMA_MAP)
153 - Unmap DMA buffer (DFL_FPGA_PORT_DMA_UNMAP)
154 - Reset AFU (DFL_FPGA_PORT_RESET)
155 - Get number of irqs of port error (DFL_FPGA_PORT_ERR_GET_IRQ_NUM)
156 - Set interrupt trigger for port error (DFL_FPGA_PORT_ERR_SET_IRQ)
157 - Get number of irqs of UINT (DFL_FPGA_PORT_UINT_GET_IRQ_NUM)
158 - Set interrupt trigger for UINT (DFL_FPGA_PORT_UINT_SET_IRQ)
166 User-space applications can also mmap() accelerator MMIO regions.
169 (/sys/class/fpga_region/<regionX>/<dfl-port.m>/):
176 detected by the hardware, and clear the logged errors.
184 +----------+ +--------+ +--------+ +--------+
187 +----------+ +--------+ +--------+ +--------+
188 +-----------------------+
191 +-----------------------+
192 ------------------------------------------------------------------
193 +----------------------------+
196 +----------------------------+
197 +------------------------+
198 | FPGA Hardware Device |
199 +------------------------+
208 The FPGA DFL Device could be different hardware, e.g. PCIe device, platform
229 Similar to the FME driver, the FPGA Accelerated Function Unit (AFU) driver is
253 FPGA virtualization - PCIe SRIOV
264 +-------------------------------+ +-------------+
266 +-------------------------------+ +-------------+
269 +-----|------------|---------|--------------|-------+
271 | +-----+ +-------+ +-------+ +-------+ |
273 | +-----+ +-------+ +-------+ +-------+ |
276 | +-------+ +------+ +-------+ |
278 | +-------+ +------+ +-------+ |
281 +---------------------------------------------------+
293 +-------++------++------+ |
297 +-------++------++------+ |
298 +-----------------------+ +--------+ | +--------+
301 +-----------------------+ +--------+ | +--------+
302 +-----------------------+ | +-----------------------+
305 +-----------------------+ | +-----------------------+
306 +------------------+ | +------------------+
308 +------------------+ Host | Machine +------------------+
309 -------------------------------------- | ------------------------------
310 +---------------+ | +---------------+
312 +---------------+ | +---------------+
364 (e.g. "dfl-port.n" or "dfl-fme.m" is found), then it's the base
369 /sys/class/fpga_region/region0/dfl-fme.0
370 /sys/class/fpga_region/region0/dfl-port.0
371 /sys/class/fpga_region/region0/dfl-port.1
374 /sys/class/fpga_region/region3/dfl-fme.1
375 /sys/class/fpga_region/region3/dfl-port.2
376 /sys/class/fpga_region/region3/dfl-port.3
381 /sys/class/fpga_region/<regionX>/<dfl-fme.n>/
382 /sys/class/fpga_region/<regionX>/<dfl-port.m>/
389 /sys/class/fpga_region/<regionX>/<dfl-fme.n>/dev
390 /sys/class/fpga_region/<regionX>/<dfl-port.n>/dev
396 supports several independent, system-wide, device counter sets in hardware to
402 Different FPGA devices may have different counter sets, depending on hardware
404 use "perf list" to check which perf events are supported by target hardware.
432 $# perf stat -a -e dfl_fme0/fab_mmio_read/ <command>
434 $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0xff/ <command>
436 $# perf stat -a -e dfl_fme0/config=0xff2006/ <command>
444 $# perf stat -a -e dfl_fme0/fab_port_mmio_read,portid=0x0/ <command>
446 $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0x0/ <command>
448 $# perf stat -a -e dfl_fme0/config=0x2006/ <command>
451 events (fab_port_*) actually share one set of counters in hardware, so it can't
455 $# perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,\
467 since they are system-wide counters on FPGA device.
502 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
520 +----------------------------+
522 +----------------------------+
524 +----------------------------+
526 +----------------------------+
528 +----------------------------+
537 The purpose of an FPGA is to be reprogrammed with newly developed hardware
538 components. New hardware can instantiate a new private feature in the DFL, and
542 * Users may need to run some diagnostic test for their hardware.
544 * Some hardware is designed for specific purposes and does not fit into one of
552 has no irq in hardware. So the interrupt handling is not added in this driver.