Lines Matching +full:system +full:- +full:on +full:- +full:a +full:- +full:chip
5 This provides an overview of GPIO access conventions on Linux.
11 What is a GPIO?
13 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
14 digital signal. They are provided from many kinds of chip, and are familiar
16 represents a bit connected to a particular pin, or "ball" on Ball Grid Array
21 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
22 non-dedicated pin can be configured as a GPIO; and most chips have at least
25 often have a few such pins to help with pin scarcity on SOCs; and there are
27 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
32 - Output values are writable (high=1, low=0). Some chips also have
34 value might be driven ... supporting "wire-OR" and similar schemes
37 - Input values are likewise readable (1, 0). Some chips support readback
38 of pins configured as "output", which is very useful in such "wire-OR"
40 input de-glitch/debounce logic, sometimes with software controls.
42 - Inputs can often be used as IRQ signals, often edge triggered but
43 sometimes level triggered. Such IRQs may be configurable as system
44 wakeup events, to wake the system from a low power state.
46 - Usually a GPIO will be configurable as either input or output, as needed
49 - Most GPIOs can be accessed while holding spinlocks, but those accessed
50 through a serial bus normally can't. Some systems support both types.
52 On a given board each GPIO is used for one specific purpose like monitoring
54 a LED, configuring a transceiver, bitbanging a serial bus, poking a hardware
55 watchdog, sensing a switch, and so on.
60 Note that this is called a "convention" because you don't need to do it this
62 is not the main issue; GPIOs are often used for the kind of board-specific
64 used on a board that's wired differently. Only least-common-denominator
65 functionality can be very portable. Other features are platform-specific,
69 One platform might implement it as simple inline functions accessing chip
76 That said, if the convention is supported on their platform, drivers should
79 standard GPIO calls should have Kconfig entries which depend on GPIOLIB. The
80 GPIO calls are available, either as "real code" or as optimized-away stubs,
88 Note that these operations include I/O barriers on platforms which need to
93 -----------------
96 "not available on this board", or indicating faults. Code that doesn't
100 for the GPIO lines so that board-specific setup code directly corresponds
103 board-specific pin configuration data (along with other board specific
106 So for example one platform uses numbers 32-159 for GPIOs; while another
107 uses numbers 0..63 with one set of GPIO controllers, 64-79 with another
108 type of GPIO controller, and on one particular board 80-95 with an FPGA.
110 use numbers 2000-2063 to identify GPIOs in a bank of I2C GPIO expanders.
112 If you want to initialize a structure with an invalid GPIO number, use
113 some negative number (perhaps "-EINVAL"); that will never be valid. To
114 test if such number from such a structure could reference a GPIO, you
119 A number that's not valid will be rejected by calls which may request
121 example, a number might be valid but temporarily unused on a given board.
123 Whether a platform supports multiple GPIO controllers is a platform-specific
129 -----------
130 The first thing a system should do with a GPIO is allocate it, using
133 One of the next things to do with a GPIO, often in board setup code when
134 setting up a platform_device using the GPIO, is mark its direction::
140 The return value is zero for success, else a negative errno. It should
143 a task context. However, for spinlock-safe GPIOs it's OK to use them
147 This helps avoid signal glitching during system startup.
150 of a GPIO implicitly requests that GPIO (see below) if it has not been
155 that particular GPIO can't be used in that mode. It's generally a bad
156 idea to rely on boot firmware to have set the direction correctly, since
158 that board setup code probably needs to multiplex that pin as a GPIO,
162 Spinlock-Safe GPIO access
163 -------------------------
178 value of an output pin, the value returned should be what's seen on the
180 issues including open-drain signaling and output latencies.
188 Platform-specific implementations are encouraged to optimize the two
190 output, value) are constant. It's normal for them to need only a couple
191 of instructions in such cases (reading or writing a hardware register),
193 applications a lot more efficient (in both space and time) than spending
194 dozens of instructions on subroutine calls.
198 --------------------------
201 get to the head of a queue to transmit a command and get its response.
205 by returning nonzero from this call (which requires a valid GPIO number,
210 To access such GPIOs, a different set of accessors is defined::
219 Accessing such GPIOs requires a context which may sleep, for example
220 a threaded IRQ handler, and those accessors must be used instead of
221 spinlock-safe accessors without the cansleep() name suffix.
224 on GPIOs that can't be accessed from hardIRQ handlers, these calls act
225 the same as the spinlock-safe calls.
229 controller chip too (These setup calls are usually made from board
246 ----------------------------
247 To help catch system configuration errors, two calls are defined::
250 * non-null labels may be useful for diagnostics.
254 /* release previously-claimed GPIO */
260 a task context. However, for spinlock-safe GPIOs it's OK to request GPIOs
265 several hundred potential GPIOs, but often only a dozen are used on any
267 (a) two or more drivers wrongly think they have exclusive use of that
269 needed to manage a signal that's in active use. That is, requesting a
270 GPIO can serve as a kind of lock.
273 power management, such as by powering down unused chip sectors and, more
277 be informed of their use; a gpiolib driver's .request() operation may call
278 pinctrl_gpio_request(), and a gpiolib driver's .free() operation may call
279 pinctrl_gpio_free(). The pinctrl subsystem allows a pinctrl_gpio_request()
280 to succeed concurrently with a pin or pingroup being "owned" by a device for
284 GPIO signal to the appropriate pin should occur within a GPIO driver's
286 setup of an output GPIO's value. This allows a glitch-free migration from a
287 pin's special function to GPIO. This is sometimes required when using a GPIO
288 to implement a workaround on signals typically driven by a non-GPIO HW block.
297 Also note that it's your responsibility to have stopped using a GPIO
303 /* request a single GPIO, with initial configuration specified by
309 /* request multiple GPIOs in a single call
313 /* release multiple GPIOs in a single call
319 * GPIOF_DIR_IN - to configure direction as input
320 * GPIOF_DIR_OUT - to configure direction as output
322 * GPIOF_INIT_LOW - as output, set initial level to LOW
323 * GPIOF_INIT_HIGH - as output, set initial level to HIGH
324 * GPIOF_OPEN_DRAIN - gpio pin is open drain type.
325 * GPIOF_OPEN_SOURCE - gpio pin is open source type.
327 * GPIOF_EXPORT_DIR_FIXED - export gpio to sysfs, keep direction
328 * GPIOF_EXPORT_DIR_CHANGEABLE - also export, allow changing direction
333 * GPIOF_IN - configure as input
334 * GPIOF_OUT_INIT_LOW - configured as output, initial level LOW
335 * GPIOF_OUT_INIT_HIGH - configured as output, initial level HIGH
339 require to connect pull-up on such pins. By enabling this flag, gpio lib will
345 require to connect pull-down on such pin. By enabling this flag, gpio lib will
360 A typical example of usage::
363 { 32, GPIOF_OUT_INIT_HIGH, "Power LED" }, /* default to ON */
382 --------------------
394 else a negative errno code if the mapping can't be done. (For example,
395 some GPIOs can't be used as IRQs.) It is an unchecked error to use a GPIO
399 These two mapping calls are expected to cost on the order of a single
402 Non-error values returned from gpio_to_irq() can be passed to request_irq()
404 devices, by the board-specific initialization code. Note that IRQ trigger
406 system wakeup capabilities.
408 Non-error values returned from irq_to_gpio() would most commonly be used
410 when the IRQ is edge-triggered. Note that some platforms don't support
415 ----------------------------
418 "open collector" is used for TTL.) A pullup resistor causes the high signal
419 level. This is sometimes called a "wire-AND"; or more practically, from the
420 negative logic (low=true) perspective this is a "wire-OR".
422 One common example of an open drain signal is a shared active-low IRQ line.
427 there's a common idiom you can use to emulate it with any GPIO pin that can
436 If you are "driving" the signal high but gpio_get_value(gpio) reports a low
439 common example, that's how I2C clocks are stretched: a slave that needs a
445 ------------------------------------------
447 A GPIO controller on a SOC might be tightly coupled with the pinctrl
450 case where e.g. a GPIO controller need to reserve a pin or set the
451 direction of a pin by calling any of::
458 But how does the pin control subsystem cross-correlate the GPIO
459 numbers (which are a global business) to a certain pin on a certain
463 cross-reference tables. These are described in
464 Documentation/driver-api/pin-control.rst
468 that different pin ranges in a SoC is managed by different gpio drivers.
480 For non-DT support, user can call gpiochip_add_pin_range() with appropriate
481 parameters to register a range of gpio pins with a pinctrl driver. For this
489 this is highly chip-specific and nonportable. One platform might not need
492 to route a given GPIO to any one of several pins. (Yes, those examples all
496 pulldowns integrated on some platforms. Not all platforms support them,
498 pullups (or pulldowns) so that the on-chip ones should not be used.
499 (When a circuit needs 5 kOhm, on-chip 100 kOhm resistors won't do.)
500 Likewise drive strength (2 mA vs 20 mA) and voltage (1.8V vs 3.3V) is a
501 platform-specific issue, as are models like (not) having a one-to-one
504 There are other system-specific mechanisms that are not specified here,
505 like the aforementioned options for input de-glitching and wire-OR output.
508 commonly grouped in banks of 16 or 32, with a given SOC having several such
510 from pins not managed as GPIOs. Code relying on such mechanisms will
514 a side effect of configuring an add-on board with some GPIO expanders.
523 As a debugging aid, if debugfs is available a /sys/kernel/debug/gpio file
529 -----------------------------
530 In this framework each GPIO controller is packaged as a "struct gpio_chip"
533 - methods to establish GPIO direction
534 - methods used to access GPIO values
535 - flag saying whether calls to its methods may sleep
536 - optional debugfs dump method (showing extra state like pullup config)
537 - label for diagnostics
539 There is also per-instance data, which may come from device.platform_data:
542 The code implementing a gpio_chip should support multiple instances of the
544 gpio_chip and issue gpiochip_add(). Removing a GPIO controller should be
547 Most often a gpio_chip is part of an instance-specific structure with state
549 and more. Chips such as codecs will have complex non-GPIO state.
557 ----------------
558 To force-enable this framework, a platform's Kconfig will "select" GPIOLIB,
561 It may also provide a custom value for ARCH_NR_GPIOS, so that it better
562 reflects the number of GPIOs in actual use on that platform, without
563 wasting static table space. (It should count both built-in/SoC GPIOs and
564 also ones on GPIO expanders.
567 GPIOs through GPIO-lib and the code cannot be enabled by the user.
577 logic optimizing access to specific SOC-based GPIOs. For example, if the
581 code, costing at least a few dozen instructions. For bitbanged I/O, such
584 For SOCs, platform-specific code defines and registers gpio_chip instances
585 for each bank of on-chip GPIOs. Those GPIOs should be numbered/labeled to
586 match chip vendor documentation, and directly match board schematics. They
587 may well start at zero and go up to a platform-specific limit. Such GPIOs
593 -------------
594 For external GPIO controllers -- such as I2C or SPI expanders, ASICs, multi
595 function devices, FPGAs or CPLDs -- most often board-specific code handles
598 platform-specific GPIOs.
601 of GPIOs that chip will expose, and passes them to each GPIO expander chip
602 using platform_data. Then the chip driver's probe() routine could pass that
605 Initialization order can be important. For example, when a device relies on
606 an I2C-based GPIO, its probe() routine should only be called after that GPIO
618 configure a sysfs user interface to GPIOs. This is different from the
620 value instead of just showing a gpio state summary. Plus, it could be
621 present on production systems without debugging support.
623 Given appropriate hardware documentation for the system, userspace could
625 protect boot loader segments in flash memory. System upgrade procedures
626 may need to temporarily remove that protection, first importing a GPIO,
627 then changing its output state, then updating the code before re-enabling
631 Again depending on appropriate hardware documentation, on some systems
632 userspace GPIO can be used to determine system configuration data that
634 GPIO drivers could be all that the system really needs.
637 GPIO tasks: "leds-gpio" and "gpio_keys", respectively. Use those
643 --------------
646 - Control interfaces used to get userspace control over GPIOs;
648 - GPIOs themselves; and
650 - GPIO controllers ("gpio_chip" instances).
654 The control interfaces are write-only:
659 a GPIO to userspace by writing its number to this file.
661 Example: "echo 19 > export" will create a "gpio19" node
666 Example: "echo 19 > unexport" will remove a "gpio19"
681 doesn't support changing the direction of a GPIO, or
689 If the pin can be configured as interrupt-generating interrupt
691 description of "edge"), you can poll(2) on that file and
696 new value or close the file and re-open it to read the value.
700 that will make poll(2) on the "value" file return.
714 read-only attributes:
718 "base" ... same as N, the first GPIO managed by this chip
722 "ngpio" ... how many GPIOs this manges (N to N + ngpio - 1)
725 what purposes. However, those numbers are not always stable; GPIOs on
726 a daughtercard might be different depending on the base board being used,
729 the correct GPIO number to use for a given signal.
733 --------------------------
743 /* create a sysfs link to an exported GPIO node */
747 After a kernel driver requests a GPIO, it may only be made available in
750 from accidentally clobbering important system state.
753 of experiments easier), or can provide an always-there interface that's
754 suitable for documenting as part of a board support package.
759 a descriptive name.
768 .. kernel-doc:: drivers/gpio/gpiolib-legacy.c