Lines Matching +full:gcc +full:- +full:sc7280
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manu Gautam <mgautam@codeaurora.org>
15 - enum:
16 - qcom,msm8996-dwc3
17 - qcom,msm8998-dwc3
18 - qcom,sc7180-dwc3
19 - qcom,sc7280-dwc3
20 - qcom,sdm660-dwc3
21 - qcom,sdm845-dwc3
22 - qcom,sdx55-dwc3
23 - qcom,sm4250-dwc3
24 - qcom,sm6115-dwc3
25 - qcom,sm8150-dwc3
26 - qcom,sm8250-dwc3
27 - qcom,sm8350-dwc3
28 - const: qcom,dwc3
34 "#address-cells":
37 "#size-cells":
42 power-domains:
48 A list of phandle and clock-specifier pairs for the clocks
49 listed in clock-names.
51 - description: System Config NOC clock.
52 - description: Master/Core clock, has to be >= 125 MHz
54 - description: System bus AXI clock.
55 - description: Mock utmi clock needed for ITP/SOF generation
57 - description: Sleep clock, used for wakeup when
60 clock-names:
62 - const: cfg_noc
63 - const: core
64 - const: iface
65 - const: mock_utmi
66 - const: sleep
68 assigned-clocks:
70 - description: Phandle and clock specifier of MOCK_UTMI_CLK.
71 - description: Phandle and clock specifoer of MASTER_CLK.
73 assigned-clock-rates:
75 - description: Must be 19.2MHz (19200000).
76 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
83 interconnect-names:
85 - const: usb-ddr
86 - const: apps-usb
90 - description: The interrupt that is asserted
92 - description: The interrupt that is asserted
94 - description: Wakeup event on DM line.
95 - description: Wakeup event on DP line.
97 interrupt-names:
99 - const: hs_phy_irq
100 - const: ss_phy_irq
101 - const: dm_hs_phy_irq
102 - const: dp_hs_phy_irq
104 qcom,select-utmi-as-pipe-clk:
114 "^usb@[0-9a-f]+$":
118 - compatible
119 - reg
120 - "#address-cells"
121 - "#size-cells"
122 - ranges
123 - power-domains
124 - clocks
125 - clock-names
126 - interrupts
127 - interrupt-names
132 - |
133 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
134 #include <dt-bindings/interrupt-controller/arm-gic.h>
135 #include <dt-bindings/interrupt-controller/irq.h>
137 #address-cells = <2>;
138 #size-cells = <2>;
141 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
144 #address-cells = <2>;
145 #size-cells = <2>;
147 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
148 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
149 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
150 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
151 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
152 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
155 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
156 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
157 assigned-clock-rates = <19200000>, <150000000>;
163 interrupt-names = "hs_phy_irq", "ss_phy_irq",
166 power-domains = <&gcc USB30_PRIM_GDSC>;
168 resets = <&gcc GCC_USB30_PRIM_BCR>;
178 phy-names = "usb2-phy", "usb3-phy";