Lines Matching +full:imx8mp +full:- +full:dwc3
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: NXP iMX8MP Soc USB Controller
11 - Li Jun <jun.li@nxp.com>
15 const: fsl,imx8mp-dwc3
20 dwc3 core on the SOC.
22 "#address-cells":
25 "#size-cells":
28 dma-ranges:
41 A list of phandle and clock-specifier pairs for the clocks
42 listed in clock-names.
44 - description: system hsio root clock.
45 - description: suspend clock, used for usb wakeup logic.
47 clock-names:
49 - const: hsio
50 - const: suspend
55 "^usb@[0-9a-f]+$":
56 $ref: snps,dwc3.yaml#
59 - compatible
60 - reg
61 - "#address-cells"
62 - "#size-cells"
63 - dma-ranges
64 - ranges
65 - clocks
66 - clock-names
67 - interrupts
72 - |
73 #include <dt-bindings/clock/imx8mp-clock.h>
74 #include <dt-bindings/interrupt-controller/arm-gic.h>
76 compatible = "fsl,imx8mp-dwc3";
80 clock-names = "hsio", "suspend";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
88 compatible = "snps,dwc3";
93 clock-names = "bus_early", "ref", "suspend";
94 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
95 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
96 assigned-clock-rates = <500000000>;
99 phy-names = "usb2-phy", "usb3-phy";
100 snps,dis-u2-freeclk-exists-quirk;