Lines Matching +full:inter +full:- +full:processor

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Palmer Dabbelt <palmer@dabbelt.com>
11   - Anup Patel <anup.patel@wdc.com>
14   SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15   Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16   interrupts. It directly connects to the timer and inter-processor interrupt
17   lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19   The clock frequency of CLINT is specified via "timebase-frequency" DT
20   property of "/cpus" DT node. The "timebase-frequency" DT property is
26       - enum:
27           - sifive,fu540-c000-clint
28           - canaan,k210-clint
29       - const: sifive,clint0
32       Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
33       Supported compatible strings are -
34       "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
35       onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
39       Please refer to sifive-blocks-ip-versioning.txt for details
44   interrupts-extended:
50   - compatible
51   - reg
52   - interrupts-extended
55   - |
57       compatible = "sifive,fu540-c000-clint", "sifive,clint0";
58       interrupts-extended = <&cpu1intc 3 &cpu1intc 7