Lines Matching +full:imx7ulp +full:- +full:clock

10   - compatible		: Compatible list, contains "fsl,vf610-sai",
11 			  "fsl,imx6sx-sai", "fsl,imx6ul-sai",
12 			  "fsl,imx7ulp-sai", "fsl,imx8mq-sai",
13 			  "fsl,imx8qm-sai", "fsl,imx8mm-sai",
14 			  "fsl,imx8mn-sai", "fsl,imx8mp-sai", or
15 			  "fsl,imx8ulp-sai".
17   - reg			: Offset and length of the register set for the device.
19   - clocks		: Must contain an entry for each entry in clock-names.
21   - clock-names		: Must include the "bus" for register access and
22 			  "mclk1", "mclk2", "mclk3" for bit clock and frame
23 			  clock providing.
24   - dmas		: Generic dma devicetree binding as described in
27   - dma-names		: Two dmas have to be defined, "tx" and "rx".
29   - pinctrl-names	: Must contain a "default" entry.
31   - pinctrl-NNN		: One property must exist for each entry in
32 			  pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
35   - lsb-first		: Configures whether the LSB or the MSB is transmitted
40   - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
46   - fsl,sai-asynchronous: This is a boolean property. If present, indicating
54   - big-endian		: Boolean property, required if all the SAI
55 			  registers are big-endian rather than little-endian.
59   - fsl,sai-mclk-direction-output: This is a boolean property. If present,
60 			 indicates that SAI will output the SAI MCLK clock.
63 - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
67 - fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
71 	      compatible = "fsl,vf610-sai";
73 	      pinctrl-names = "default";
74 	      pinctrl-0 = <&pinctrl_sai2_1>;
78 	      clock-names = "bus", "mclk1", "mclk2", "mclk3";
79 	      dma-names = "tx", "rx";
82 	      big-endian;
83 	      lsb-first;