Lines Matching +full:big +full:- +full:endian

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Shengjiu Wang <shengjiu.wang@nxp.com>
20       - fsl,imx35-spdif
21       - fsl,vf610-spdif
22       - fsl,imx6sx-spdif
23       - fsl,imx8qm-spdif
24       - fsl,imx8qxp-spdif
25       - fsl,imx8mq-spdif
26       - fsl,imx8mm-spdif
27       - fsl,imx8mn-spdif
28       - fsl,imx8ulp-spdif
38       - description: DMA controller phandle and request line for RX
39       - description: DMA controller phandle and request line for TX
41   dma-names:
43       - const: rx
44       - const: tx
48       - description: The core clock of spdif controller.
49       - description: Clock for tx0 and rx0.
50       - description: Clock for tx1 and rx1.
51       - description: Clock for tx2 and rx2.
52       - description: Clock for tx3 and rx3.
53       - description: Clock for tx4 and rx4.
54       - description: Clock for tx5 and rx5.
55       - description: Clock for tx6 and rx6.
56       - description: Clock for tx7 and rx7.
57       - description: The spba clock is required when SPDIF is placed as a bus
63   clock-names:
65       - const: core
66       - const: rxtx0
67       - const: rxtx1
68       - const: rxtx2
69       - const: rxtx3
70       - const: rxtx4
71       - const: rxtx5
72       - const: rxtx6
73       - const: rxtx7
74       - const: spba
77   big-endian:
80       If this property is absent, the native endian mode will be in use
81       as default, or the big endian mode will be in use for all the device
82       registers. Set this flag for HCDs with big endian descriptors and big
83       endian registers.
86   - compatible
87   - reg
88   - interrupts
89   - dmas
90   - dma-names
91   - clocks
92   - clock-names
97   - |
99         compatible = "fsl,imx35-spdif";
104         dma-names = "rx", "tx";
110         clock-names = "core", "rxtx0",
115         big-endian;