Lines Matching +full:gcc +full:- +full:sdm845
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Mukesh Savaliya <msavaliy@codeaurora.org>
11 - Akash Asthana <akashast@codeaurora.org>
24 - qcom,geni-se-qup
30 clock-names:
32 - const: m-ahb
33 - const: s-ahb
37 - description: Master AHB Clock
38 - description: Slave AHB Clock
40 "#address-cells":
43 "#size-cells":
51 interconnect-names:
52 const: qup-core
58 - compatible
59 - reg
60 - clock-names
61 - clocks
62 - "#address-cells"
63 - "#size-cells"
64 - ranges
67 "^.*@[0-9a-f]+$":
77 clock-names:
88 interconnect-names:
91 - const: qup-core
92 - const: qup-config
93 - const: qup-memory
96 - reg
97 - clock-names
98 - clocks
100 "spi@[0-9a-f]+$":
106 $ref: /spi/spi-controller.yaml#
111 - qcom,geni-spi
116 "#address-cells":
119 "#size-cells":
123 - compatible
124 - interrupts
125 - "#address-cells"
126 - "#size-cells"
128 "i2c@[0-9a-f]+$":
131 $ref: /schemas/i2c/i2c-controller.yaml#
136 - qcom,geni-i2c
141 "#address-cells":
144 "#size-cells":
147 clock-frequency:
152 - compatible
153 - interrupts
154 - "#address-cells"
155 - "#size-cells"
157 "serial@[0-9a-f]+$":
165 - qcom,geni-uart
166 - qcom,geni-debug-uart
171 - description: UART core irq
172 - description: Wakeup irq (RX GPIO)
175 - compatible
176 - interrupts
181 - |
182 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
183 #include <dt-bindings/interrupt-controller/arm-gic.h>
186 #address-cells = <2>;
187 #size-cells = <2>;
190 compatible = "qcom,geni-se-qup";
192 clock-names = "m-ahb", "s-ahb";
193 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
194 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
195 #address-cells = <2>;
196 #size-cells = <2>;
200 compatible = "qcom,geni-i2c";
203 clock-names = "se";
204 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
205 pinctrl-names = "default", "sleep";
206 pinctrl-0 = <&qup_1_i2c_5_active>;
207 pinctrl-1 = <&qup_1_i2c_5_sleep>;
208 #address-cells = <1>;
209 #size-cells = <0>;
213 compatible = "qcom,geni-uart";
216 clock-names = "se";
217 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
218 pinctrl-names = "default", "sleep";
219 pinctrl-0 = <&qup_1_uart_3_active>;
220 pinctrl-1 = <&qup_1_uart_3_sleep>;