Lines Matching +full:overrun +full:- +full:throttle +full:- +full:ms
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - if:
16 - required:
17 - aspeed,lpc-io-reg
18 - required:
19 - aspeed,lpc-interrupts
20 - required:
21 - aspeed,sirq-polarity-sense
25 const: aspeed,ast2500-vuart
26 - if:
29 const: mrvl,mmp-uart
32 reg-shift:
35 - reg-shift
36 - if:
41 - enum:
42 - ns8250
43 - ns16450
44 - ns16550
45 - ns16550a
48 - required: [ clock-frequency ]
49 - required: [ clocks ]
54 - const: ns8250
55 - const: ns16450
56 - const: ns16550
57 - const: ns16550a
58 - const: ns16850
59 - const: aspeed,ast2400-vuart
60 - const: aspeed,ast2500-vuart
61 - const: intel,xscale-uart
62 - const: mrvl,pxa-uart
63 - const: nuvoton,wpcm450-uart
64 - const: nuvoton,npcm750-uart
65 - const: nvidia,tegra20-uart
66 - const: nxp,lpc3220-uart
67 - items:
68 - enum:
69 - exar,xr16l2552
70 - exar,xr16l2551
71 - exar,xr16l2550
72 - const: ns8250
73 - items:
74 - enum:
75 - altr,16550-FIFO32
76 - altr,16550-FIFO64
77 - altr,16550-FIFO128
78 - fsl,16550-FIFO64
79 - fsl,ns16550
80 - andestech,uart16550
81 - nxp,lpc1850-uart
82 - opencores,uart16550-rtlsvn105
83 - ti,da830-uart
84 - const: ns16550a
85 - items:
86 - enum:
87 - ns16750
88 - cavium,octeon-3860-uart
89 - xlnx,xps-uart16550-2.00.b
90 - ralink,rt2880-uart
91 - enum:
92 - ns16550 # Deprecated, unless the FIFO really is broken
93 - ns16550a
94 - items:
95 - enum:
96 - ralink,mt7620a-uart
97 - ralink,rt3052-uart
98 - ralink,rt3883-uart
99 - const: ralink,rt2880-uart
100 - enum:
101 - ns16550 # Deprecated, unless the FIFO really is broken
102 - ns16550a
103 - items:
104 - enum:
105 - mediatek,mt7622-btif
106 - mediatek,mt7623-btif
107 - const: mediatek,mtk-btif
108 - items:
109 - const: mrvl,mmp-uart
110 - const: intel,xscale-uart
111 - items:
112 - enum:
113 - nvidia,tegra30-uart
114 - nvidia,tegra114-uart
115 - nvidia,tegra124-uart
116 - nvidia,tegra186-uart
117 - nvidia,tegra194-uart
118 - nvidia,tegra210-uart
119 - const: nvidia,tegra20-uart
127 clock-frequency: true
135 current-speed:
139 reg-offset:
143 reg-shift:
146 reg-io-width:
149 device. There are some systems that require 32-bit accesses to the
152 used-by-rtas:
158 no-loopback-test:
163 fifo-size:
167 auto-flow-control:
174 tx-threshold:
179 overrun-throttle-ms:
181 How long to pause uart rx when input overrun is encountered.
183 rts-gpios: true
184 cts-gpios: true
185 dtr-gpios: true
186 dsr-gpios: true
187 rng-gpios: true
188 dcd-gpios: true
190 aspeed,sirq-polarity-sense:
191 $ref: /schemas/types.yaml#/definitions/phandle-array
193 Phandle to aspeed,ast2500-scu compatible syscon alongside register
196 applicable to aspeed,ast2500-vuart.
199 aspeed,lpc-io-reg:
202 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
204 aspeed,lpc-interrupts:
205 $ref: "/schemas/types.yaml#/definitions/uint32-array"
209 A 2-cell property describing the VUART SIRQ number and SIRQ
211 applicable to aspeed,ast2500-vuart.
214 - reg
215 - interrupts
220 - |
225 reg-shift = <2>;
226 clock-frequency = <48000000>;
228 - |
229 #include <dt-bindings/gpio/gpio.h>
234 clock-frequency = <48000000>;
235 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
236 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
237 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
238 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
239 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
240 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
242 - |
243 #include <dt-bindings/clock/aspeed-clock.h>
244 #include <dt-bindings/interrupt-controller/irq.h>
246 compatible = "aspeed,ast2500-vuart";
248 reg-shift = <2>;
251 no-loopback-test;
252 aspeed,lpc-io-reg = <0x3f8>;
253 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;