Lines Matching +full:cache +full:- +full:unified

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive L2 Cache Controller
11   - Sagar Kadam <sagar.kadam@sifive.com>
12   - Yash Shah <yash.shah@sifive.com>
13   - Paul Walmsley  <paul.walmsley@sifive.com>
16   The SiFive Level 2 Cache Controller is used to provide access to fast copies
17   of memory for masters in a Core Complex. The Level 2 Cache Controller also
18   acts as directory-based coherency manager.
22   - $ref: /schemas/cache-controller.yaml#
29           - sifive,fu540-c000-ccache
30           - sifive,fu740-c000-ccache
33     - compatible
38       - enum:
39           - sifive,fu540-c000-ccache
40           - sifive,fu740-c000-ccache
41       - const: cache
43   cache-block-size:
46   cache-level:
49   cache-sets:
52   cache-size:
55   cache-unified: true
60       - description: DirError interrupt
61       - description: DataError interrupt
62       - description: DataFail interrupt
63       - description: DirFail interrupt
68   next-level-cache: true
70   memory-region:
73       The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
74       The reserved memory node should be defined as per the bindings in reserved-memory.txt.
80         const: sifive,fu540-c000-ccache
99   - compatible
100   - cache-block-size
101   - cache-level
102   - cache-sets
103   - cache-size
104   - cache-unified
105   - interrupts
106   - reg
109   - |
110     cache-controller@2010000 {
111         compatible = "sifive,fu540-c000-ccache", "cache";
112         cache-block-size = <64>;
113         cache-level = <2>;
114         cache-sets = <1024>;
115         cache-size = <2097152>;
116         cache-unified;
118         interrupt-parent = <&plic0>;
122         next-level-cache = <&L25>;
123         memory-region = <&l2_lim>;