Lines Matching +full:tlb +full:- +full:split
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
30 - sifive,rocket0
31 - sifive,bullet0
32 - sifive,e5
33 - sifive,e7
34 - sifive,e51
35 - sifive,e71
36 - sifive,u54-mc
37 - sifive,u74-mc
38 - sifive,u54
39 - sifive,u74
40 - sifive,u5
41 - sifive,u7
42 - canaan,k210
43 - const: riscv
44 - const: riscv # Simulator only
46 Identifies that the hart uses the RISC-V instruction set
49 mmu-type:
52 hart. These values originate from the RISC-V Privileged
57 - riscv,sv32
58 - riscv,sv39
59 - riscv,sv48
60 - riscv,none
64 Identifies the specific RISC-V instruction set architecture
65 supported by the hart. These are documented in the RISC-V
66 User-Level ISA document, available from
74 - rv64imac
75 - rv64imafdc
77 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
78 timebase-frequency: false
80 interrupt-controller:
85 '#interrupt-cells':
89 const: riscv,cpu-intc
91 interrupt-controller: true
94 - '#interrupt-cells'
95 - compatible
96 - interrupt-controller
99 - riscv,isa
100 - interrupt-controller
105 - |
108 #address-cells = <1>;
109 #size-cells = <0>;
110 timebase-frequency = <1000000>;
112 clock-frequency = <0>;
115 i-cache-block-size = <64>;
116 i-cache-sets = <128>;
117 i-cache-size = <16384>;
120 cpu_intc0: interrupt-controller {
121 #interrupt-cells = <1>;
122 compatible = "riscv,cpu-intc";
123 interrupt-controller;
127 clock-frequency = <0>;
129 d-cache-block-size = <64>;
130 d-cache-sets = <64>;
131 d-cache-size = <32768>;
132 d-tlb-sets = <1>;
133 d-tlb-size = <32>;
135 i-cache-block-size = <64>;
136 i-cache-sets = <64>;
137 i-cache-size = <32768>;
138 i-tlb-sets = <1>;
139 i-tlb-size = <32>;
140 mmu-type = "riscv,sv39";
143 tlb-split;
144 cpu_intc1: interrupt-controller {
145 #interrupt-cells = <1>;
146 compatible = "riscv,cpu-intc";
147 interrupt-controller;
152 - |
155 #address-cells = <1>;
156 #size-cells = <0>;
162 mmu-type = "riscv,sv48";
163 interrupt-controller {
164 #interrupt-cells = <1>;
165 interrupt-controller;
166 compatible = "riscv,cpu-intc";