Lines Matching +full:irq +full:- +full:push +full:- +full:pull
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
26 - st,stm32h743-pinctrl
27 - st,stm32mp135-pinctrl
28 - st,stm32mp157-pinctrl
29 - st,stm32mp157-z-pinctrl
31 '#address-cells':
33 '#size-cells':
37 pins-are-numbered: true
45 - Phandle to the syscon node which includes IRQ mux selection.
46 - The offset of the IRQ mux selection register.
47 - The field mask of IRQ mux, needed if different of 0xf.
48 $ref: "/schemas/types.yaml#/definitions/phandle-array"
53 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
58 '^gpio@[0-9a-f]*$':
61 gpio-controller: true
62 '#gpio-cells':
72 gpio-ranges:
81 st,bank-name:
86 - GPIOA
87 - GPIOB
88 - GPIOC
89 - GPIOD
90 - GPIOE
91 - GPIOF
92 - GPIOG
93 - GPIOH
94 - GPIOI
95 - GPIOJ
96 - GPIOK
97 - GPIOZ
99 st,bank-ioport:
108 - gpio-controller
109 - '#gpio-cells'
110 - reg
111 - clocks
112 - st,bank-name
114 '-[0-9]*$':
126 $ref: "/schemas/types.yaml#/definitions/uint32-array"
130 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
133 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
134 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
135 - function: The function number, can be:
145 - include/dt-bindings/pinctrl/stm32-pinfunc.h
160 bias-disable:
162 bias-pull-down:
164 bias-pull-up:
166 drive-push-pull:
168 drive-open-drain:
170 output-low:
172 output-high:
174 slew-rate:
184 - pinmux
187 - compatible
188 - '#address-cells'
189 - '#size-cells'
190 - ranges
191 - pins-are-numbered
196 - |
197 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
198 #include <dt-bindings/mfd/stm32f4-rcc.h>
201 #address-cells = <1>;
202 #size-cells = <1>;
203 compatible = "st,stm32f429-pinctrl";
205 pins-are-numbered;
208 gpio-controller;
209 #gpio-cells = <2>;
213 st,bank-name = "GPIOA";
217 //Example 2 (using gpio-ranges)
219 #address-cells = <1>;
220 #size-cells = <1>;
221 compatible = "st,stm32f429-pinctrl";
223 pins-are-numbered;
226 gpio-controller;
227 #gpio-cells = <2>;
231 st,bank-name = "GPIOB";
232 gpio-ranges = <&pinctrl 0 0 16>;
236 gpio-controller;
237 #gpio-cells = <2>;
241 st,bank-name = "GPIOC";
243 gpio-ranges = <&pinctrl 0 16 3>,
250 usart1_pins_a: usart1-0 {
253 bias-disable;
254 drive-push-pull;
255 slew-rate = <0>;
259 bias-disable;
265 pinctrl-0 = <&usart1_pins_a>;
266 pinctrl-names = "default";