Lines Matching +full:phy +full:- +full:names
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7280-qmp-usb3-dp-phy
18 - qcom,sc8180x-qmp-usb3-dp-phy
19 - qcom,sdm845-qmp-usb3-dp-phy
20 - qcom,sm8250-qmp-usb3-dp-phy
23 - description: Address and length of PHY's USB serdes block.
24 - description: Address and length of the DP_COM control block.
25 - description: Address and length of PHY's DP serdes block.
27 reg-names:
29 - const: usb
30 - const: dp_com
31 - const: dp
33 "#clock-cells":
36 "#address-cells":
39 "#size-cells":
46 - description: Phy aux clock.
47 - description: Phy config clock.
48 - description: 19.2 MHz ref clk.
49 - description: Phy common block aux clock.
51 clock-names:
53 - const: aux
54 - const: cfg_ahb
55 - const: ref
56 - const: com_aux
60 - description: reset of phy block.
61 - description: phy common block reset.
63 reset-names:
65 - const: phy
66 - const: common
68 vdda-phy-supply:
70 Phandle to a regulator supply to PHY core block.
72 vdda-pll-supply:
74 Phandle to 1.8V regulator supply to PHY refclk pll block.
76 vddp-ref-clk-supply:
82 "^usb3-phy@[0-9a-f]+$":
85 The USB3 PHY.
90 - description: Address and length of TX.
91 - description: Address and length of RX.
92 - description: Address and length of PCS.
93 - description: Address and length of TX2.
94 - description: Address and length of RX2.
95 - description: Address and length of pcs_misc.
99 - description: pipe clock
101 clock-names:
103 - const: pipe0
105 clock-output-names:
107 - const: usb3_phy_pipe_clk_src
109 '#clock-cells':
112 '#phy-cells':
116 - reg
117 - clocks
118 - clock-names
119 - '#clock-cells'
120 - '#phy-cells'
122 "^dp-phy@[0-9a-f]+$":
125 The DP PHY.
130 - description: Address and length of TX.
131 - description: Address and length of RX.
132 - description: Address and length of PCS.
133 - description: Address and length of TX2.
134 - description: Address and length of RX2.
136 '#clock-cells':
139 '#phy-cells':
143 - reg
144 - '#clock-cells'
145 - '#phy-cells'
148 - compatible
149 - reg
150 - "#clock-cells"
151 - "#address-cells"
152 - "#size-cells"
153 - ranges
154 - clocks
155 - clock-names
156 - resets
157 - reset-names
158 - vdda-phy-supply
159 - vdda-pll-supply
164 - |
165 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
166 usb_1_qmpphy: phy-wrapper@88e9000 {
167 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
171 reg-names = "usb", "dp_com", "dp";
172 #clock-cells = <1>;
173 #address-cells = <1>;
174 #size-cells = <1>;
181 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
185 reset-names = "phy", "common";
187 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
188 vdda-pll-supply = <&vdda_usb2_ss_core>;
190 usb3-phy@200 {
197 #clock-cells = <0>;
198 #phy-cells = <0>;
200 clock-names = "pipe0";
201 clock-output-names = "usb3_phy_pipe_clk_src";
204 dp-phy@88ea200 {
210 #clock-cells = <1>;
211 #phy-cells = <0>;