Lines Matching full:description

13 description:
58       - description: Address and length of PHY's common serdes block.
59       - description: Address and length of PHY's DP_COM control block.
89     description:
93     description:
97     description:
104     description:
135             - description: Phy aux clock.
136             - description: Phy config clock.
137             - description: 19.2 MHz ref clk.
138             - description: Phy common block aux clock.
147             - description: reset of phy block.
148             - description: phy common block reset.
163             - description: Phy aux clock.
164             - description: Phy config clock.
165             - description: 19.2 MHz ref clk.
173             - description: reset of phy block.
174             - description: phy common block reset.
189             - description: Phy aux clock.
190             - description: Phy config clock.
191             - description: 19.2 MHz ref clk.
199             - description: reset of phy block.
200             - description: phy common block reset.
201             - description: phy's ahb cfg block reset.
220             - description: Phy aux clock.
221             - description: Phy config clock.
222             - description: 19.2 MHz ref clk.
230             - description: reset of phy block.
231             - description: phy common block reset.
246             - description: 19.2 MHz ref clk.
252             - description: PHY reset in the UFS controller.
269             - description: 19.2 MHz ref clk.
270             - description: Phy reference aux clock.
277             - description: PHY reset in the UFS controller.
291             - description: pipe clk.
297             - description: reset of phy block.
298             - description: phy common block reset.
313             - description: Phy aux clock.
314             - description: Phy config clock.
321             - description: reset of phy block.
322             - description: phy common block reset.
343             - description: Phy aux clock.
344             - description: Phy config clock.
345             - description: 19.2 MHz ref clk.
346             - description: Phy refgen clk.
355             - description: reset of phy block.
372             - description: Phy aux clock.
373             - description: 19.2 MHz ref clk source.
374             - description: 19.2 MHz ref clk.
375             - description: Phy common block aux clock.
384             - description: reset of phy block.
385             - description: phy common block reset.
401             - description: Phy aux clock.
402             - description: 19.2 MHz ref clk.
403             - description: Phy common block aux clock.
411             - description: reset of phy block.
412             - description: phy common block reset.