Lines Matching +full:drive +full:- +full:strength +full:- +full:microamp
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
19 pattern: "^dsi-phy@[0-9a-f]+$"
23 - items:
24 - enum:
25 - mediatek,mt7623-mipi-tx
26 - const: mediatek,mt2701-mipi-tx
27 - const: mediatek,mt2701-mipi-tx
28 - const: mediatek,mt8173-mipi-tx
29 - const: mediatek,mt8183-mipi-tx
36 - description: PLL reference clock
38 clock-output-names:
41 "#phy-cells":
44 "#clock-cells":
47 nvmem-cells:
52 nvmem-cell-names:
54 - const: calibration-data
56 drive-strength-microamp:
64 - compatible
65 - reg
66 - clocks
67 - clock-output-names
68 - "#phy-cells"
69 - "#clock-cells"
74 - |
75 #include <dt-bindings/clock/mt8173-clk.h>
76 dsi-phy@10215000 {
77 compatible = "mediatek,mt8173-mipi-tx";
80 clock-output-names = "mipi_tx0_pll";
81 drive-strength-microamp = <4000>;
82 nvmem-cells= <&mipi_tx_calibration>;
83 nvmem-cell-names = "calibration-data";
84 #clock-cells = <0>;
85 #phy-cells = <0>;