Lines Matching +full:gcc +full:- +full:ipq8074
3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
16 - "qcom,pcie-sm8250" for sm8250
17 - "qcom,pcie-ipq6018" for ipq6018
19 - reg:
21 Value type: <prop-encoded-array>
22 Definition: Register ranges as listed in the reg-names property
24 - reg-names:
28 - "parf" Qualcomm specific registers
29 - "dbi" DesignWare PCIe registers
30 - "elbi" External local bus interface registers
31 - "config" PCIe configuration space
32 - "atu" ATU address space (optional)
34 - device_type:
37 Definition: Should be "pci". As specified in snps,dw-pcie.yaml
39 - #address-cells:
42 Definition: Should be 3. As specified in snps,dw-pcie.yaml
44 - #size-cells:
47 Definition: Should be 2. As specified in snps,dw-pcie.yaml
49 - ranges:
51 Value type: <prop-encoded-array>
52 Definition: As specified in snps,dw-pcie.yaml
54 - interrupts:
56 Value type: <prop-encoded-array>
59 - interrupt-names:
64 - #interrupt-cells:
67 Definition: Should be 1. As specified in snps,dw-pcie.yaml
69 - interrupt-map-mask:
71 Value type: <prop-encoded-array>
72 Definition: As specified in snps,dw-pcie.yaml
74 - interrupt-map:
76 Value type: <prop-encoded-array>
77 Definition: As specified in snps,dw-pcie.yaml
79 - clocks:
81 Value type: <prop-encoded-array>
83 in clock-names property
85 - clock-names:
89 - "iface" Configuration AHB clock
91 - clock-names:
95 - "core" Clocks the pcie hw block
96 - "phy" Clocks the pcie PHY block
97 - "aux" Clocks the pcie AUX block
98 - "ref" Clocks the pcie ref block
99 - clock-names:
103 - "aux" Auxiliary (AUX) clock
104 - "bus_master" Master AXI clock
105 - "bus_slave" Slave AXI clock
107 - clock-names:
111 - "pipe" Pipe Clock driving internal logic
112 - "aux" Auxiliary (AUX) clock
113 - "cfg" Configuration clock
114 - "bus_master" Master AXI clock
115 - "bus_slave" Slave AXI clock
117 - clock-names:
118 Usage: required for ipq8074
121 - "iface" PCIe to SysNOC BIU clock
122 - "axi_m" AXI Master clock
123 - "axi_s" AXI Slave clock
124 - "ahb" AHB clock
125 - "aux" Auxiliary clock
127 - clock-names:
131 - "iface" PCIe to SysNOC BIU clock
132 - "axi_m" AXI Master clock
133 - "axi_s" AXI Slave clock
134 - "axi_bridge" AXI bridge clock
135 - "rchng"
137 - clock-names:
141 - "iface" AHB clock
142 - "aux" Auxiliary clock
143 - "master_bus" AXI Master clock
144 - "slave_bus" AXI Slave clock
146 - clock-names:
150 - "aux" Auxiliary clock
151 - "cfg" Configuration clock
152 - "bus_master" Master AXI clock
153 - "bus_slave" Slave AXI clock
154 - "slave_q2a" Slave Q2A clock
155 - "tbu" PCIe TBU clock
156 - "pipe" PIPE clock
158 - clock-names:
162 - "aux" Auxiliary clock
163 - "cfg" Configuration clock
164 - "bus_master" Master AXI clock
165 - "bus_slave" Slave AXI clock
166 - "slave_q2a" Slave Q2A clock
167 - "tbu" PCIe TBU clock
168 - "ddrss_sf_tbu" PCIe SF TBU clock
169 - "pipe" PIPE clock
171 - resets:
173 Value type: <prop-encoded-array>
175 in reset-names property
177 - reset-names:
181 - "axi" AXI reset
182 - "ahb" AHB reset
183 - "por" POR reset
184 - "pci" PCI reset
185 - "phy" PHY reset
187 - reset-names:
191 - "core" Core reset
193 - reset-names:
197 - "axi_m" AXI master reset
198 - "axi_s" AXI slave reset
199 - "pipe" PIPE reset
200 - "axi_m_vmid" VMID reset
201 - "axi_s_xpu" XPU reset
202 - "parf" PARF reset
203 - "phy" PHY reset
204 - "axi_m_sticky" AXI sticky reset
205 - "pipe_sticky" PIPE sticky reset
206 - "pwr" PWR reset
207 - "ahb" AHB reset
208 - "phy_ahb" PHY AHB reset
209 - "ext" EXT reset
211 - reset-names:
212 Usage: required for ipq8074
215 - "pipe" PIPE reset
216 - "sleep" Sleep reset
217 - "sticky" Core Sticky reset
218 - "axi_m" AXI Master reset
219 - "axi_s" AXI Slave reset
220 - "ahb" AHB Reset
221 - "axi_m_sticky" AXI Master Sticky reset
223 - reset-names:
227 - "pipe" PIPE reset
228 - "sleep" Sleep reset
229 - "sticky" Core Sticky reset
230 - "axi_m" AXI Master reset
231 - "axi_s" AXI Slave reset
232 - "ahb" AHB Reset
233 - "axi_m_sticky" AXI Master Sticky reset
234 - "axi_s_sticky" AXI Slave Sticky reset
236 - reset-names:
240 - "axi_m" AXI Master reset
241 - "axi_s" AXI Slave reset
242 - "axi_m_sticky" AXI Master Sticky reset
243 - "pipe_sticky" PIPE sticky reset
244 - "pwr" PWR reset
245 - "ahb" AHB reset
247 - reset-names:
251 - "pci" PCIe core reset
253 - power-domains:
255 Value type: <prop-encoded-array>
260 - vdda-supply:
265 - vdda_phy-supply:
270 - vdda_refclk-supply:
275 - vddpe-3v3-supply:
280 - phys:
283 Definition: List of phandle(s) as listed in phy-names property
285 - phy-names:
290 - <name>-gpios:
292 Value type: <prop-encoded-array>
294 - "perst-gpios" PCIe endpoint reset signal line
295 - "wake-gpios" PCIe endpoint wake signal line
299 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
304 reg-names = "dbi", "elbi", "parf", "config";
306 linux,pci-domain = <0>;
307 bus-range = <0x00 0xff>;
308 num-lanes = <1>;
309 #address-cells = <3>;
310 #size-cells = <2>;
314 interrupt-names = "msi";
315 #interrupt-cells = <1>;
316 interrupt-map-mask = <0 0 0 0x7>;
317 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
321 clocks = <&gcc PCIE_A_CLK>,
322 <&gcc PCIE_H_CLK>,
323 <&gcc PCIE_PHY_CLK>,
324 <&gcc PCIE_AUX_CLK>,
325 <&gcc PCIE_ALT_REF_CLK>;
326 clock-names = "core", "iface", "phy", "aux", "ref";
327 resets = <&gcc PCIE_ACLK_RESET>,
328 <&gcc PCIE_HCLK_RESET>,
329 <&gcc PCIE_POR_RESET>,
330 <&gcc PCIE_PCI_RESET>,
331 <&gcc PCIE_PHY_RESET>,
332 <&gcc PCIE_EXT_RESET>;
333 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
334 pinctrl-0 = <&pcie_pins_default>;
335 pinctrl-names = "default";
340 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
345 reg-names = "parf", "dbi", "elbi", "config";
347 linux,pci-domain = <0>;
348 bus-range = <0x00 0xff>;
349 num-lanes = <1>;
350 #address-cells = <3>;
351 #size-cells = <2>;
355 interrupt-names = "msi";
356 #interrupt-cells = <1>;
357 interrupt-map-mask = <0 0 0 0x7>;
358 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
362 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
363 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
364 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
365 <&gcc GCC_PCIE_0_AUX_CLK>;
366 clock-names = "iface", "master_bus", "slave_bus", "aux";
367 resets = <&gcc GCC_PCIE_0_BCR>;
368 reset-names = "core";
369 power-domains = <&gcc PCIE0_GDSC>;
370 vdda-supply = <&pma8084_l3>;
372 phy-names = "pciephy";
373 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
374 pinctrl-0 = <&pcie0_pins_default>;
375 pinctrl-names = "default";