Lines Matching +full:pcie +full:- +full:host +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
17 const: microchip,pcie-host-1.0 # PolarFire
22 reg-names:
24 - const: cfg
25 - const: apb
28 minItems: 1
30 - description: PCIe host controller
31 - description: builtin MSI controller
33 interrupt-names:
34 minItems: 1
36 - const: pcie
37 - const: msi
40 maxItems: 1
42 msi-controller:
45 msi-parent:
49 - reg
50 - reg-names
51 - "#interrupt-cells"
52 - interrupts
53 - interrupt-map-mask
54 - interrupt-map
55 - msi-controller
60 - |
62 #address-cells = <2>;
63 #size-cells = <2>;
64 pcie0: pcie@2030000000 {
65 compatible = "microchip,pcie-host-1.0";
68 reg-names = "cfg", "apb";
70 #address-cells = <3>;
71 #size-cells = <2>;
72 #interrupt-cells = <1>;
74 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
75 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
76 <0 0 0 2 &pcie_intc0 1>,
79 interrupt-parent = <&plic0>;
80 msi-parent = <&pcie0>;
81 msi-controller;
82 bus-range = <0x00 0x7f>;
84 pcie_intc0: interrupt-controller {
85 #address-cells = <0>;
86 #interrupt-cells = <1>;
87 interrupt-controller;