Lines Matching +full:interrupt +full:- +full:map
4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 - device_type: Must be "pci"
11 - reg: Base addresses and lengths of the root ports.
12 - reg-names: Names of the above areas to use during resource lookup.
13 - #address-cells: Address representation for root ports (must be 3)
14 - #size-cells: Size representation for root ports (must be 2)
15 - clocks: Must contain an entry for each entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names:
19 - sys_ckN :transaction layer and data link layer clock
21 - free_ck :for reference clock of PCIe subsys
23 - ahb_ckN :AHB slave interface operating clock for CSR access and RC
26 - axi_ckN :application layer MMIO channel operating clock
27 - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
29 - obff_ckN :OBFF functional block operating clock
30 - pipe_ckN :LTSSM and PHY/MAC layer operating clock
32 - phys: List of PHY specifiers (used by generic PHY framework).
33 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
35 - power-domains: A phandle and power domain specifier pair to the power domain
37 - bus-range: Range of bus numbers associated with this controller.
38 - ranges: Ranges for the PCI memory and I/O regions.
41 - #interrupt-cells: Size representation for interrupts (must be 1)
42 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
45 - resets: Must contain an entry for each entry in reset-names.
47 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
51 -interrupts: A list of interrupt outputs of the controller, must have one
53 - interrupt-names: Must include the following entries:
54 - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received
55 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
57 In addition, the device tree node must have sub-nodes describing each
61 - device_type: Must be "pci"
62 - reg: Only the first four bytes are used to refer to the correct bus number
64 - #address-cells: Must be 3
65 - #size-cells: Must be 2
66 - #interrupt-cells: Must be 1
67 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
70 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
76 compatible = "mediatek,mt7623-hifsys",
77 "mediatek,mt2701-hifsys",
80 #clock-cells = <1>;
81 #reset-cells = <1>;
85 compatible = "mediatek,mt7623-pcie";
91 reg-names = "subsys", "port0", "port1", "port2";
92 #address-cells = <3>;
93 #size-cells = <2>;
94 #interrupt-cells = <1>;
95 interrupt-map-mask = <0xf800 0 0 0>;
96 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
103 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
107 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
110 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
111 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
112 bus-range = <0x00 0xff>;
118 #address-cells = <3>;
119 #size-cells = <2>;
120 #interrupt-cells = <1>;
121 interrupt-map-mask = <0 0 0 0>;
122 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
128 #address-cells = <3>;
129 #size-cells = <2>;
130 #interrupt-cells = <1>;
131 interrupt-map-mask = <0 0 0 0>;
132 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
138 #address-cells = <3>;
139 #size-cells = <2>;
140 #interrupt-cells = <1>;
141 interrupt-map-mask = <0 0 0 0>;
142 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
150 compatible = "mediatek,mt2712-pcie";
153 reg-names = "port1";
154 linux,pci-domain = <1>;
155 #address-cells = <3>;
156 #size-cells = <2>;
158 interrupt-names = "pcie_irq";
161 clock-names = "sys_ck1", "ahb_ck1";
163 phy-names = "pcie-phy1";
164 bus-range = <0x00 0xff>;
168 #interrupt-cells = <1>;
169 interrupt-map-mask = <0 0 0 7>;
170 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
174 pcie_intc1: interrupt-controller {
175 interrupt-controller;
176 #address-cells = <0>;
177 #interrupt-cells = <1>;
182 compatible = "mediatek,mt2712-pcie";
185 reg-names = "port0";
186 linux,pci-domain = <0>;
187 #address-cells = <3>;
188 #size-cells = <2>;
190 interrupt-names = "pcie_irq";
193 clock-names = "sys_ck0", "ahb_ck0";
195 phy-names = "pcie-phy0";
196 bus-range = <0x00 0xff>;
200 #interrupt-cells = <1>;
201 interrupt-map-mask = <0 0 0 7>;
202 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
206 pcie_intc0: interrupt-controller {
207 interrupt-controller;
208 #address-cells = <0>;
209 #interrupt-cells = <1>;
216 compatible = "mediatek,mt7622-pcie";
219 reg-names = "port0";
220 linux,pci-domain = <0>;
221 #address-cells = <3>;
222 #size-cells = <2>;
224 interrupt-names = "pcie_irq";
231 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
234 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
235 bus-range = <0x00 0xff>;
239 #interrupt-cells = <1>;
240 interrupt-map-mask = <0 0 0 7>;
241 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
245 pcie_intc0: interrupt-controller {
246 interrupt-controller;
247 #address-cells = <0>;
248 #interrupt-cells = <1>;
253 compatible = "mediatek,mt7622-pcie";
256 reg-names = "port1";
257 linux,pci-domain = <1>;
258 #address-cells = <3>;
259 #size-cells = <2>;
261 interrupt-names = "pcie_irq";
269 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
272 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
273 bus-range = <0x00 0xff>;
277 #interrupt-cells = <1>;
278 interrupt-map-mask = <0 0 0 7>;
279 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
283 pcie_intc1: interrupt-controller {
284 interrupt-controller;
285 #address-cells = <0>;
286 #interrupt-cells = <1>;