Lines Matching +full:non +full:- +full:prefetchable
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
24 "fsl,ls1028a-pcie"
26 "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
27 "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
28 "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
29 "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"
30 - reg: base addresses and lengths of the PCIe controller register blocks.
31 - interrupts: A list of interrupt outputs of the controller. Must contain an
32 entry for each entry in the interrupt-names property.
33 - interrupt-names: Must include the following entries:
35 - fsl,pcie-scfg: Must include two entries.
39 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
46 compatible = "fsl,ls1021a-pcie";
49 reg-names = "regs", "config";
51 interrupt-names = "intr";
52 fsl,pcie-scfg = <&scfg 0>;
53 #address-cells = <3>;
54 #size-cells = <2>;
56 dma-coherent;
57 num-lanes = <4>;
58 bus-range = <0x0 0xff>;
60 0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */
61 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
62 #interrupt-cells = <1>;
63 interrupt-map-mask = <0 0 0 7>;
64 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,