Lines Matching +full:ethernet +full:- +full:phy
1 XILINX AXI ETHERNET Device Tree Bindings
2 --------------------------------------------------------
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
5 provides connectivity to an external ethernet PHY supporting different
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
27 instead, and only the Ethernet core interrupt is optionally
29 - phy-handle : Should point to the external phy device.
30 See ethernet.txt file in the same directory.
31 - xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
34 - phy-mode : See ethernet.txt
35 - xlnx,phy-type : Deprecated, do not use, but still accepted in preference
36 to phy-mode.
37 - xlnx,txcsum : 0 or empty for disabling TX checksum offload,
40 - xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload
41 - xlnx,switch-x-sgmii : Boolean to indicate the Ethernet core is configured to
42 support both 1000BaseX and SGMII modes. If set, the phy-mode
45 - clock-names: Tuple listing input clock names. Possible clocks:
47 axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS interfaces
48 ref_clk: Ethernet reference clock, used by signal delay
51 PCS/PMA PHY)
55 specified, the clock rate is auto-detected from the CPU clock
57 trees should specify all applicable clocks by name - the
60 - clocks: Phandles to input clocks matching clock-names. Refer to common
62 - axistream-connected: Reference to another node which contains the resources
64 If this is specified, the DMA-related resources from that
67 - mdio : Child node for MDIO bus. Must be defined if PHY access is
69 unless the PHY is accessed through a different bus).
72 axi_ethernet_eth: ethernet@40c00000 {
73 compatible = "xlnx,axi-ethernet-1.00.a";
75 interrupt-parent = <µblaze_0_axi_intc>;
77 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
79 phy-mode = "mii";
84 phy-handle = <&phy0>;
86 #address-cells = <1>;
87 #size-cells = <0>;
88 phy0: phy@0 {
89 device_type = "ethernet-phy";